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preliminary cyw43340 single-chip, dual-band (2.4 gh z/5 ghz) ieee 802.11 a/b/g/n mac/baseband/radio with in tegrated bluetooth 4.0 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14943 rev. *l revised tuesday, march 28, 2017 general description the cypress cyw43340 single?chip quad?radio device provides the hig hest level of integration for w earables, internet of things and gateway applications, with int egrated dual band (2.4 ghz / 5 ghz) ieee 802.1 1 a/b/g and single?stream ieee 802.11n mac/ baseband/radio, and bluetooth 4.0. the cyw4 3340 includes integrated power amplifiers and lnas for the 2.4 ghz and 5 ghz wlan bands, and an integrated 2.4 ghz t/r switch. this greatly reduces the external part co unt, pcb footprint, and cost of the soluti on. using advanced design techniques and process technology to reduc e active and idle power, the cyw43340 is designed to address the needs of mobile devices that require minimal power consumption and compac t size. it includes a power management unit which simplifies the system power topology and allows for operation dire ctly from a mobile platform battery while maximizing battery life. the cyw43340 implements the highly sophist icated enhanced collaborative coexistenc e algorithms and ha rdware mechanisms, allowing for an extremely collaborative bluetoo th coexistence scheme along with coexiste nce support for external radios (such a s cellular and lte, gps, wimax, and ultra?wideband) and a sing le shared 2.4 ghz antenna for bl uetooth and wlan. as a result, enhanced overall quality for simultaneous vo ice, video, and data transmission in an io t or wearable application is achieved. for the wlan section, two host interface opt ions are included: an sdio v2.0 interface and a high-speed inter-chip (hsic) interf ace (a usb 2.0 derivative for short-distance on- board connections). an independent, high-spe ed uart is provided for the bluetooth h ost interface. cypress part numbering scheme cypress is converting the acquired iot part numbers from broadcom to the cypress par t numbering scheme. due to this conversion, there is no change in form, fit, or function as a result of offe ring the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in cypress documents, go to http://www.cypress.com/glossary . feautures ieee 802.11x key features dual?band 2.4 ghz and 5 ghz ieee 802.11 a/b/g/n single?stream ieee 802.11n su pport for 20 mhz and 40 mhz channels provides phy layer rates up to 150 mbps for typical upper?layer throughput in excess of 90 mbps. supports the ieee 802.11n stbc (space?time block coding) rx and ldpc (low?density parity check) tx options for improved range and power efficiency. supports a single 2.4 ghz antenna shared between wlan and bluetooth. shared bluetooth and 2.4 ghz wlan receive signal path elimi- nates the need for an external power splitter while maintaining excellent sensitivity for both bluetooth and wlan. internal fractional npll allows support for a wide range of reference clock frequencies supports ieee 802.15.2 external coexistence interface to optimize bandwidth utilization with other co?located wireless technologies such as gps, wimax, or uwb supports standard sdio v2.0 host interfaces. alternative host interface supports hsic v1.0 (short?distance usb device) integrated arm? cortex?m3? processor and on?chip memory for complete wlan subsystem functionality, minimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. on?chip memory includes 512 kb sram and 640 kb rom. onedriver? software architec ture for easy migration from existing embedded wlan and bluetooth devices as well as future devices. table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM43340 cyw43340 BCM43340xkubg cyw43340xkubg BCM43340hkubg cyw43340hkubg
document number: 002-14943 rev. *l page 2 of 96 preliminary cyw43340 bluetooth key features complies with bluetooth core sp ecification version 4.0 with provisions for supporting future specifications. bluetooth class 1 or class 2 transmitter operation supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets. adaptive frequency hopping (afh) for reducing radio frequency interference interface support: host controlle r interface (hci) using a high- speed uart interface and pcm for audio data low power consumption improves battery life of handheld devices. supports multiple simultaneous advanced audio distribution profiles (a2dp) for stereo sound. automatic frequency detection for standard crystal and tcxo values general features supports battery voltage range from 2.9v to 4.8v supplies with internal switching regulator. programmable dynamic power management 3072-bit otp for storing board parameters routable on low?cost 1x1 pcb stack?ups 141-ball wlbga package(5.67 mm 4.47 mm, 0.4 mm pitch) security: ? wpa? and wpa2? (personal) support for powerful encryp- tion and authentication ? aes in wlan hardware for fast er data encryption and ieee 802.11i compatibility ? reference wlan subsystem provides cisco? compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0) ? reference wlan subsystem provides wi?fi protected set- up (wps) worldwide regulatory support: gl obal products supported with worldwide homologated design figure 1. functi onal block diagram iot resources cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrate the device into y our design. cypress provides cust omer access to a wide range of information, including technical documentation, schematic diagra ms, product bill of materials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ). vio vbat cyw43340 wlan ? host ? i/f bluetooth host ? i/f wl_reg_on sdio* wl_irq bt_reg_on uart bt_dev_wake bt_host_wake clk_req hsic pcm/i 2 s 2.4 ? ghz ? wlan ? + ? bluetooth ? tx/rx cbf fem ? or t/r ? switch 5 ? ghz ? wlan ? tx 5 ? ghz ? wlan ? rx
document number: 002-14943 rev. *l page 3 of 96 preliminary cyw43340 contents 1. introduction ................................................................... 4 1.1 overview ............................................................... 4 1.2 features ................................................................ 5 1.3 standards compliance .......................................... 6 2. power supplies an d power management ................... 7 2.1 power supply topology ........................................ 7 2.2 wlan power management . .............. ........... ......... 9 2.3 pmu sequencing ............. .............. .............. ......... 9 2.4 power-off shutdown ........................................... 10 2.5 power-up/power-down/rese t circuits ............... 10 3. frequency references ............................................... 11 3.1 crystal interface and clock generation .............. 11 3.2 tcxo .................................................................. 11 3.3 frequency selection ......... .............. .............. ....... 13 3.4 external 32.768 khz low-power oscillator ......... 14 4. bluetooth subsystem overview ................................ 15 4.1 features .............................................................. 15 4.2 bluetooth radio ................................................... 16 5. bluetooth baseband core ... .............. .............. .......... 17 5.1 bluetooth 4.0 features ........................................ 17 5.2 link control layer ............................................... 17 5.3 test mode support ........... .............. .............. ....... 17 5.4 bluetooth power management unit ......... ............ 18 5.5 adaptive frequency hoppin g .............................. 21 5.6 advanced bluetooth/wlan coexistence ............ 21 5.7 fast connection (interlaced page and inquiry scans) .............. .............. ........... ....... 21 6. microprocessor and memory unit for bluetooth ..... 22 6.1 ram, rom, and patch memory .......................... 22 6.2 reset ................................................................... 22 7. bluetooth peripheral transport unit ........................ 23 7.1 pcm interface ..................................................... 23 7.2 uart interface .................................................... 30 7.3 i 2 s interface ........................................................ 31 8. wlan global functions ............................................ 34 8.1 wlan cpu and memory subsystem ...... ............ 34 8.2 one-time programmable memory ...................... 34 8.3 gpio interface .................................................... 34 8.4 external coexistence interface ........................... 34 8.5 uart interface .................................................... 35 8.6 jtag interface .................................................... 35 9. wlan host interfaces ................................................ 36 9.1 sdio v2.0 ............................................................ 36 9.2 hsic interface ..................................................... 38 10. wireless lan mac and phy ................................... 39 10.1 mac features ................................................... 39 10.2 wlan phy descr iption ..................................... 42 11. wlan radio subsystem .......................................... 44 11.1 receiver path .................................................... 44 11.2 transmit path .............. ...................................... 44 11.3 calibration ......................................................... 44 12. pinout and signal descriptions .............................. 45 12.1 signal assignments ........................................... 45 12.2 signal descriptions ........ .................................... 45 12.3 i/o states .......................................................... 54 13. dc characteristics ................................................... 57 13.1 absolute maximum rati ngs ............................... 57 13.2 environmental ratings .. .................................... 57 13.3 electrostatic discharge specifications .............. 58 13.4 recommended operating conditions and dc characteristics ....................................... 58 14. bluetooth rf specifications .................................... 60 15. wlan rf specifications .......................................... 67 15.1 introduction ........................................................ 67 15.2 2.4 ghz band general rf specifications ......... 68 15.3 wlan 2.4 ghz receiver performance specifications ................................ 68 15.4 wlan 2.4 ghz transmitter performance specifications ................................ 72 15.5 wlan 5 ghz receiver performance specifications ................................ 73 15.6 wlan 5 ghz transmitter performance specifications ................................ 75 15.7 general spurious emissions specifications ...... 76 16. internal regulator electri cal specifications .......... 77 16.1 core buck switching re gulator ......................... 77 16.2 3.3v ldo (ldo3p3) ......................................... 78 16.3 2.5v ldo (ldo2p5) ......................................... 79 16.4 hsicdvdd ldo ............................................... 79 16.5 cldo ................................................................ 80 16.6 lnldo .............................................................. 81 17. system power consumption ................................... 82 17.1 wlan current consumption ............................. 82 17.2 bluetooth, and ble current consumption ........ 83 18. interface timing and ac characteristics ............... 84 18.1 sdio timing ............... ....................................... 84 18.2 hsic interface specifications ............................ 86 18.3 jtag timing ..................................................... 86 19. power-up sequence and timing ............................. 87 19.1 sequencing of reset and regulator control signals . .................................. 87 20. package information ............ .............. .............. ........ 90 20.1 package thermal characte ristics ....... .............. 90 20.2 junction temperature estimation and psi jt versus theta jc ............................... 90 20.3 environmental characteri stics ........................... 90 21. mechanical information ........................................... 91 22. ordering information ................................................ 93 document history ........................................................... 94 sales, solutions, and legal information ...................... 96
document number: 002-14943 rev. *l page 4 of 96 preliminary cyw43340 1. introduction 1.1 overview the cypress cyw43340 single-chip device provides the highest leve l of integration for wearables, audio and iot applications, wi th integrated ieee 802.1 a/b/g/n mac/ baseband/radio, and bluetooth 4.0. it provides a small form-factor solution with minimal extern al components to drive down cost, flexibility in size, form, and f unction. comprehensive power management circuitry and software e nsure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 2 shows the interconnect of all the major physical blocks in the cyw43340 and their associated ex ternal interfaces, which are described in greater detail in the following sections. figure 2. block diagram chip common bt rf modem axi backplane armcm3 axi2ahb ahb2axi sdiod usb20d hsic dot11mac (d11) 1x1 11n phy 2.4 ghz / 5 ghz dualband radio socsram ram512kb rom640kb ahb bus matrix uart armcm3 wlan master slave fm receiver ram rom i 2 s pcm port control rx/tx lcu apu bluerf ble axi2apb dma jtag master ahb2apb timers gpio wd pause registers shared lna control wlan bt access arm cm0 ram rom swp dig ahb bridge analog pmu pmu controller clb jtag from wlan bt to wlan bt pmu xtal/radio/pads etc wlan bt/fm gci from wlan bt to wlan bt fll clk rst to clb to clb to gci lte lte clb upi
document number: 002-14943 rev. *l page 5 of 96 preliminary cyw43340 1.2 features the cyw43340 supports the following wlan and bluetooth features: ieee 802.11a/b/g/n dual -band radio with internal power am plifiers, lnas, and t/r switches bluetooth v4.0 with integrated class 1 pa concurrent bluetooth, and wlan operation on-chip wlan driver execution capabl e of supporting ieee 802.11 functionality single- and dual-antenna support ? single antenna with shared lna ? simultaneous bt/wlan receive with single antenna wlan host interface options: ? sdio v2.0, including default and high-speed timing. ? hsic (usb device interface for sh ort distance on-board applications) bt host digital interface (can be used concurrently with above interfaces): ? uart (up to 4 mbps) eci?enhanced coexistence support, ability to coordi nate bt sco transmissions around wlan receives i 2 s/pcm for bt audio hci high-speed uart (h4, h5) transport support wideband speech support (16 bits linear data, msb first, left just ified at 4k samples/s for transparent air coding, both throug h i 2 s and pcm interface) bluetooth smartaudio ? technology improves voice and music quality to headsets bluetooth low power inquiry and page scan bluetooth low energy (ble) support bluetooth packet loss concealment (plc) bluetooth wideband speech (wbs) audio rate-matching algorithms multiple simultaneous a2dp audio stream
document number: 002-14943 rev. *l page 6 of 96 preliminary cyw43340 1.3 standards compliance the cyw43340 supports the following standards: bluetooth 4.0 (including bluetooth low energy) ieee 802.11n?handheld device class (section 11) ieee 802.11a ieee 802.11b ieee 802.11g ieee 802.11d ieee 802.11h ieee 802.11i the cyw43340 will support the following future drafts/standards: ieee 802.11r?fast roaming (between aps) ieee 802.11k?resource management ieee 802.11w?secure management frames ieee 802.11 extensions: ? ieee 802.11e qos enhancements (as per the wmm? specification is already supported) ? ieee 802.11h 5 ghz extensions ? ieee 802.11i mac enhancements ? ieee 802.11r fast roaming support ? ieee 802.11k radio resource measurement the cyw43340 supports the following securi ty features and proprietary protocols: security: ? wep ? wpa? personal ? wpa2? personal ? wmm ? wmm-ps (u-apsd) ? wmm-sa ? wapi ? aes (hardware accelerator) ? tkip (host-computed) ? ckip (sw support) proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ieee 802.15.2 coexistence compliance?on silicon so lution compliant with ieee 3 wire requirements
document number: 002-14943 rev. *l page 7 of 96 preliminary cyw43340 2. power supplies and power management 2.1 power supply topology one buck regulator, multiple ldo regulators, and a power managem ent unit (pmu) are integrated in to the cyw43340. all regulators are programmable via the pmu. these blocks simplify powe r supply design for bluetooth, and wlan in embedded designs. a single vbat (2.9?4.8v) and vio supply (1.8v to 3.3v) can be us ed, with all additional voltages being provided by the regulato rs in the cyw43340. two control signals, bt_reg_on and wl_reg _on, are used to power-up the regulators and take the respective section out of reset. the cbuck cldo and lnldo power up when any of the re set signals are deasserted. all regulators are powered down only when both bt_reg_on and wl_reg_on are deasserted. the cldo and lnldo may be turned off/on based on the dynamic demands of the digital baseband. the cyw43340 allows for an extremely low power-consumption mode by completely shutting down the cbuck, cldo, and lndlo regulators. when in this state, lpldo1 and lpldo2 (which are low-power linear regulators that are supplied by the system vio supply) provide the cyw43340 with all the voltages it requires, further reducing leakage currents. 2.1.1 cyw43340 pmu features vbat to 1.35vout (372 ma maximum) co re-buck (cbuck) switching regulator vbat to 3.3vout (450 ma maximu m) ldo3p3 (external-capacitor) vbat to 2.5vout (70 ma maximum) ldo2p5 (external-capacitor) 1.35v to 1.2vout (100 ma maximu m) lnldo (external-capacitor) 1.35v to 1.2vout (150 ma maximu m) cldo (external-capacitor) 1.35v to 1.2vout (80 ma maximum) hsicdvdd ldo (external-capacitor) additional internal ldos (not externally accessible) figure 3 on page 8 shows the regulators and a typical power topology.
document number: 002-14943 rev. *l page 8 of 96 preliminary cyw43340 figure 3. typical power topology lnldo max 100 ma cldo max 150 ma internal lnldo internal lnldo internal lnldo internal lnldo vddio_rf for rf switches bt class 1 pa vio 1.8C3.3v otp (3.3v) 1.2v 1.2v 1.35v 1.2v loads not to power supply noise to power supply noise shaded areas are internal to the cyw43340. vbat 2.9C4.8v wl_reg_on bt_reg_on vio 1.8 C 3.3v wlbga con . shown. internal lnldo internal lnldo hsic-avdd (dfll) wl rf C afe wl rf C tx wl rf C vco, logen wl rf C lna wl rf C rx, rcal fm lna, mixer xo wl rf C synth/rf pll wl rf C bg wl otp (1.2v) bt rf wl bb pll wl digital and mem bt digital and mem always on/state ret. island clpo/ext. lpo bu + er hsic-dvdd/sdio vddio (sdio/spi, uart, coex, gpio, jtag, bt-pcm, bt-uart otp (3.3v) ipa, ipad ldo2p5 max. 70 ma 2.5v core buck regulator max. 372 ma internal lpldo1 internal lpldo2 ldo3p3 max. 450 ma 3.3v
document number: 002-14943 rev. *l page 9 of 96 preliminary cyw43340 2.2 wlan power management the cyw43340 has been designed with the stringent power consumpti on requirements of mobile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage cur rent and supply voltages. additionally, the cyw43340 integrated ram is a high vt memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the cyw43340 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides sign ificant power savings by putting the cyw43340 into various power management states appropriate to th e current environment and activities that are being performed. the power management unit enables and disables internal regulat ors, switches, and other blocks based on a computation of the required resources and a table that describes the relationship betw een resources and the time needed to enable and disable them. power up sequences are fully programmable. configurable, free-running counters (running at 32.768 khz lpo clock) in the pmu sequencer are used to turn on/turn off individual regulators and power switches. clock sp eeds are dynamically changed (or gated altogether) for the curren t mode. slower clock speeds are used wherever possible. the cyw43340 wlan power states are described as follows: active mode? all wlan blocks in the cyw43340 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. c lock speeds are dynamically adjusted by the pmu sequencer. doze mode?the radio, analog domains, and most of the linear regulator s are powered down. the rest of the cyw43340 remains powered up in an idle state. all main clocks (pll, crystal oscillat or or tcxo) are shut down to reduce active power to the mini mum. the 32.768 khz lpo clock is available only for the pmu sequencer . this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. deep-sleep mode?most of the chip including both analog and digi tal domains and most of the regulators are powered off. logic states in the digital core are saved and preserved into a retent ion memory in the always-on domain before the digital core is p owered off. upon a wake-up event triggered by the pmu timers, an external interrupt or a host resume through the hsic or sdio bus, log ic states in the digital core are restored to their pre-de ep-sleep settings to avoid lengthy hw re-initialization. power-down mode?the cyw43340 is effectively powered off by shutti ng down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. 2.3 pmu sequencing the pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required reso urces and a table that describes the relationship between resources and the time nee ded to enable and disable them. resource requests may come from several sources: clock requests from cores, the minimum resources defined in the resource min register, and the resources requested by any active resource re quest timers. the pmu sequencer maps clock requests into a set o f resources required to pro duce the requested clocks. each resource is in one of four states : enabled, disabled, transition_on, and transi tion_off and has a timer that contains 0 wh en the resource is enabled or disabled and a non-zero value in the tr ansition states. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state ch anges from transition_off to disabled or transition_on to enabled. if the time_on val ue is 0, the resource can go immediately from disabled to enabled. sim ilarly, a time_off value of 0 indicates that the resource can g o immediately from enabled to disabled. the terms enable sequence an d disable sequence refer to either the immediate transition o r the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: 1. computes the required resource set based on requests and the resource dependency table. 2. decrements all timers whose values are non zero. if a timer reac hes 0, the pmu clears the resourcepending bit for the resourc e and inverts the resourcestate bit. 3. compares the request with the current resource status and determines which re sources must be enabled or disabled. 4. initiates a disable sequence for each resource that is enabl ed, no longer being requested, and has no powered up dependents. 5. initiates an enable sequence for each res ource that is disabled, is being reques ted, and has all of its dependencies enabled.
document number: 002-14943 rev. *l page 10 of 96 preliminary cyw43340 2.4 power-off shutdown the cyw43340 provides a low-power shutdown feature that allows the device to be turn ed off while the host, and any other device s in the system, remain operational. when the cyw43340 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the cyw43340 to be effectivel y off while keeping the i/o pins powered so that they do not dr aw extra current from any other devices connected to the i/o. during a low-power shut-down stat e, provided vddio remains applied to the cyw43340, all outputs are trista ted, and most inputs signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent curren t paths or create loading on any digital signals in the system, and enables the cyw43340 to be fully integrated in an embedded device a nd take full advantage of the lowest power-savings modes. two signals on the cyw43340, the frequency reference input (wrf_x tal_cab_op) and the lpo_in input, are designed to be high- impedance inputs that do not load do wn the driving signal even if the chip does not have vddio power applied to it. when the cyw43340 is powered on from this state, it is the same as a normal power-up and the device does not retain any informa tion about its state from bef ore it was powered down. 2.5 power-up/power -down/reset circuits the cyw43340 has two signals (see table 2 ) that enable or disable the bluetoot h and wlan circuits and the internal regulator blocks, allowing the host to control power consumptio n. for timing diagrams of these signals and the required power-up sequences, see section 19.: ?power-up sequence and timing,? on page 87 . table 2. power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu (with bt_reg_on) to power up the wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw43340 regulators. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if bt_reg_on and wl_reg_on are both low, the regulators are disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on this signal is used by the pmu (with wl_reg_on) to decide whether or not to power down the internal cyw43340 regulators. if bt _reg_on and wl_reg_on are low, the r egulators will be disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by defaul t. it can be disabled through programming.
document number: 002-14943 rev. *l page 11 of 96 preliminary cyw43340 3. frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (tcxo) signal may be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. note: the crystal and tcxo implementations have different power supplies (wrf_xtal_vdd1p2 for crystal, wrf_tcxo_vdd for tcxo). 3.1 crystal interface and clock generation the cyw43340 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscill ator including all external components is shown in figure 4 . consult the reference schematics for the latest configuration. figure 4. recommended oscillator configuration a fractional-n synthesizer in t he cyw43340 gener ates the radio frequencies, clocks, and data/packet ti ming, enabling it to oper ate using a wide selection of frequency references. for sdio and hsic applications the default frequency reference is a 37.4 mhz crystal or tcxo. the signal characteristics for th e crystal interface are listed in table 3 on page 12 . note: although the fractional-n synthesizer can support alte rnative reference frequencies, frequencies other than the default require support to be added in the driver, plus addi tional extensive system testin g. contact cypress for further details. 3.2 tcxo as an alternative to a crystal, an external precision tcxo ca n be used as the frequency referenc e, provided that it meets the p hase noise requirements listed in ta b l e 3 . when the clock is provided by an external tcxo, there are two possible connection methods, as shown in figure 5 and figure 6 : 1. if the tcxo is dedicated to driving the cyw43340, it should be connected to the wrf_xtal_op pin through an external 1000 pf coupling capacitor, as shown in figure 5 . the internal clock buffer connected to this pin will be turned off when the cyw43340 goes into sleep mode. when the clock buffer turns on and off there will be a small impedance variation. if the tcxo is to be shared with another device, such as a gps receiver, and impedanc e variation is not allowed, a dedicated external clock buffer w ill be needed. power must be supplied to the wrf_xtal_vdd1p2 pin. 2. for 2.4 ghz operation only, an alternative is to dc-co uple the tcxo to the wrf_tcxo_ck pin, as shown in figure 6 . use this method when the same tcxo is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that cannot be tolerated by the other dev ice sharing the tcxo. this pin is connected to a clock buffer powered from wrf_tcxo_vdd. if the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby ensuring a constant input impedance in all states of the device. the maximum curr ent drawn from wrf_tcxo_vdd is approximately 500 a. 12?27 ? pf 12?27 ? pf wrf_xtal_on wrf_xtal_op c c x ? ohms * * ? resistor ? value ? determined ? by ? crystal ? drive ? level. ? see ? reference ? schematics ? for ? details. ?
document number: 002-14943 rev. *l page 12 of 96 preliminary cyw43340 figure 5. recommended circuit to use with an external dedicated tcxo figure 6. recommended circuit to use with an external shared tcxo table 3. crystal oscillator and external clock ? requirements and performance parameter conditions/notes crystal a external frequency reference b,c min typ max min typ max units frequency ? between 19.2 mhz and 52 mhz d,e crystal load capacitance ? ? 12 ????pf esr ? ??60??? ? drive level external cr ystal requirement 200 f ?????w input impedance (wrf_xtal_op) resistive 30k 100k ? 30k 100k ? ? capacitive ??7.5??7.5pf input impedance (wrf_tcxo_in) resistive ???30k100k? ? capacitive ?????4pf wrf_xtal_op input low level dc-coupled digital signal ???0?0.2v wrf_xtal_op input high level dc-coupled digital signal ???1.0?1.26v wrf_xtal_op input voltage ac-coupled analog signal (see figure 5 ) ???400?1200mv p-p wrf_tcxo_in input voltage dc-coupled analog signal (see figure 6 ) ???400?1980mv p-p tcxo nc 1000 ? pf wrf_xtal_op wrf_xtal_on wrf_tcxo_ck wrf_tcxo_vdd tcxo nc wrf_tcxo_ck wrf_xtal_on wrf_xtal_op to ? other ? devices wrf_tcxo_vdd to ? always ? present ? 1.8v ? supply
document number: 002-14943 rev. *l page 13 of 96 preliminary cyw43340 3.3 frequency selection any frequency within the ranges specified for the crystal and tc xo reference may be used. these include not only the standard handset reference frequencies of 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 mhz, but also other frequencies in this range, w ith approximately 80 hz resolution. the cyw43340 must have the refe rence frequency set correctly in order for any of the uart or pc m interfaces to function correctly, since all bit timing is derived from the reference frequency. note: the fractional-n synthesizer can support many refer ence frequencies. however, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. cont act cypress for further details. the reference frequency for the cyw43340 may be set in the following ways: set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. auto-detect any of the standard handset reference frequencies using an external lpo clock. for applications such as handsets and portable smart communicatio n devices, where the reference fr equency is one of the standar d frequencies commonly used, the cyw43340 aut omatically detects the reference frequen cy and programs itse lf to the correct reference frequency. in order for auto frequency detection to wo rk correctly, the cyw43340 must have a valid and stable 32.768 khz lpo clock that meets the requirements listed in table 4 on page 14 and is present during power-on reset. frequency tolerance over the lifetime of the equipment, including temperature without trimming ?20 ? 20 ?20 ? 20 ppm duty cycle 37.4 mhz clock ???405060% phase noise (802.11b/g) 37.4 mhz clock at 10 khz offset??????131dbc/hz 37.4 mhz clock at 100 khz or greater offset ??????138dbc/hz phase noise (802.11a) 37.4 mhz clock at 10 khz offset??????139dbc/hz 37.4 mhz clock at 100 khz or greater offset ??????146dbc/hz phase noise (802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset??????136dbc/hz 37.4 mhz clock at 100 khz or greater offset ??????143dbc/hz phase noise (802.11n, 5 ghz) 37.4 mhz clock at 10 khz offset??????144dbc/hz 37.4 mhz clock at 100 khz or greater offset ??????151dbc/hz a. ? (crystal) ? use ? wrf_xtal_op ? and ? wrf_xtal_on, ? internal ? power ? to ? pin ? wrf_xtal_vdd1p2. b. ? (tcxo) ? see ? ?tcxo? ? on ? page 11 ? for ? alternative ? connection ? methods. c. ? for ? a ? clock ? reference ? other ? than ? 37.4 ? mhz, ? 20 ? ? log10(f/ ? 37.4) ? db ? should ? be ? added ? to ? the ? limits, ? where ? f ? = ? the ? reference ? clock ? frequency ? in ? mhz. d. ? bt_tm6 ? should ? be ? tied ? low ? for ? a ? 52 ? mhz ? clock ? reference. ? for ? other ? frequencies, ? bt_tm6 ? should ? be ? tied ? high. ? note ? that ? 52 ? mhz ? is ? not ? an ? auto-detected frequency ? using ? the ? lpo ? clock. e. ? the ? frequency ? step ? size ? is ? approximately ? 80 ? hz ? resolution. f. ? the ? crystal ? should ? be ? capable ? of ? handling ? a ? 200uw ? drive ? level ? from ? the ? cyw43340. table 3. crystal oscillator and external clock ? requirements and performance (cont.) parameter conditions/notes crystal a external frequency reference b,c min typ max min typ max units
document number: 002-14943 rev. *l page 14 of 96 preliminary cyw43340 3.4 external 32.768 khz low-power oscillator the cyw43340 uses a secondary low frequency clock for low-power-mode timing. either the internal low-precision lpo or an extern al 32.768 khz precision oscillator is required. the internal lpo frequency range is approxima tely 33 khz 30% over process, volta ge, and temperature, which is adequate for some applications. however, a trade-off caused by this wide lpo tolerance is a small cur rent consumption increase during wlan power save mode that is incu rred by the need to wake up earlier to avoid missing beacons. whenever possible, the preferred approach for wlan is to use a precision external 32.768 khz cl ock that meets the requirements listed in table 4 . note: bt operations require the use of an exte rnal lpo that meets the requirements listed in ta b l e 4 . table 4. external 32.768 kh z sleep clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?1800 mv, p-p signal type square-wave or sine-wave ? input impedance a a.when ? power ? is ? applied ? or ? switched ? off. >100k <5 ? pf clock jitter (during initial start-up) <10,000 ppm
document number: 002-14943 rev. *l page 15 of 96 preliminary cyw43340 4. bluetooth s ubsystem overview the cypress cyw43340 is a bluetooth 4.0-comp liant, baseband processor/2.4 ghz transceiver. the cyw43340 is the optimal solution for any bluetooth voice and/or data application. the bluetooth subsystem presents a standa rd host controller interface (hci) via a high speed uart and pcm fo r audio. the cyw43340 incorporates all bluetooth 4.0 features including br/edr and le. the cyw43340 bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest in tegration into mobile handsets and portable devices. it is fully compatible with an y of the standard tcxo frequencies and provides full radio compatibility to operate simultaneously with gps, wlan, and cellular radios. the bluetooth transmitter also features a cla ss 1 power amplifier with class 2 capability. 4.1 features major bluetooth features of the cyw43340 include: supports key features of upcoming bluetooth standards fully supports bluetooth core sp ecification version 4.0 features uart baud rates up to 4 mbps supports all bluetooth 4.0 packet types supports maximum bluetooth data rates over hci uart multipoint operation with up to seven active slaves ? maximum of seven simultaneous active acl links ? maximum of three simultaneous active sco and esco connections with scatternet support trigger broadcom fast connect (tbfc) narrowband and wideband packet loss concealment scatternet operation with up to four active pico nets with background scan and support for scatter mode high-speed hci uart transport support with low-power ou t-of-band bt_dev_wake and bt_host_wake signaling (see ?host controller power management? on page 18) channel quality driven data rate and packet type selection standard bluetooth test modes extended radio and production test mode features full support for po wer savings modes ? bluetooth clock request ? bluetooth standard sniff ? deep-sleep modes and software regulator shutdown tcxo input and auto-detection of all stand ard handset clock frequencies. also support s a low-power crystal, which can be used during power save mode for better timing accuracy.
document number: 002-14943 rev. *l page 16 of 96 preliminary cyw43340 4.2 bluetooth radio the cyw43340 has an integrat ed radio transceiver that has bee n optimized for use in 2.4 ghz bl uetooth wireless systems. it has been designed to provide low-power, low-cost, robust communicatio ns for applications operating in the globally available 2.4 gh z unlicensed ism band. it is fully compliant wit h the bluetooth radio specific ation and edr specificatio n and meets or exceeds th e requirements to provide the highest communication link quality of service. 4.2.1 transmit the cyw43340 features a fully in tegrated zero-if transmitter. the baseband transmit data is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path c onsists of signal filtering, i/q upconve rsion, output power amplifier, and rf filtering. the transmitter path also incorporates ? /4?dqpsk for 2 mbps and 8?dpsk for 3 mbps to support edr. the transmitter section is com patible to the bluetooth low energy specific ation. the transmitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. 4.2.2 digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4?dqpsk, and 8?dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in th e modulation characteristics of the transmitted signal and is much more stable than direct vco modulation schemes. 4.2.3 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit- synchronization algorithm. 4.2.4 power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature- compensated design. this prov ides greater flexibility in front-end matching and filtering. due to the linear nature of the pa combined with some integrated filte ring, external filtering is required to meet t he bluetooth and regulatory harmonic and spurious requirements. for integrated mobile handset ap pli- cations in which bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. the transmitter feat ures a sophisticated on-chip transmit signal strength indicator (tssi) block to keep the absolute output power variation withi n a tight range across process, voltage, and temperature. 4.2.5 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of lin earity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology with built-in out-of-band attenuat ion enables the cyw43340 to be used in most appl ications with minimal off-chip filtering. for integrated handset operation, in whic h the bluetooth function is integrated close to the cellular transmitte r, external filtering is requir ed to eliminate the desensitiza tion of the receiver by the cellular transmit signal. 4.2.6 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. 4.2.7 receiver signal strength indicator the radio portion of the cyw43340 provides a receiver signal stre ngth indicator (rssi) signal to the baseband, so that the cont roller can take part in a bluetooth power-controlled link by providing a metric of its own receiver sig nal strength to determine wheth er the transmitter should increase or decrease its output power. 4.2.8 local oscillator generation local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high imm unity to lo pulling during pa o peration. the cyw43340 uses an internal rf and if loop filter. 4.2.9 calibration the cyw43340 radio transceiver features an automated calibration scheme that is fully se lf contained in the radio. no user inte raction is required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the perfo r- mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. this take s into account process variation and temperature variation. calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature va riations as the device cools and heats during normal operation in its environment.
document number: 002-14943 rev. *l page 17 of 96 preliminary cyw43340 5. bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time critical functions requir ed for high-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of data for all connections. it also buffers data that passes through it, handles data flow control, schedu les sco/acl tx/rx transactions, monitors bluetoot h slot usage, optimally segments and packages data into baseband packets, manages connecti on status indicators, and composes and decodes hci packets. in addition to these functions, it independently handles hci event types, and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data before sending over the air: symbol timing recovery, data deframing, forward error correction (fec), header error control (hec), cyclic redundancy check (cr c), data decryption, and data dewhi tening in the receiver. data framing, fec generation, hec generati on, crc generation, key generation, data encryption, and data whitening in the transmitter. 5.1 bluetooth 4.0 features the bbc supports all bluetooth 4.0 fe atures, with the following benefits: dual-mode classic bluetooth and classic low energy (bt and ble) operation. low energy physical layer low energy link layer enhancements to hci for low energy low energy direct test mode aes encryption note: the cyw43340 is compatible with the bluetooth low energy operating mode, which provides a dramatic reduction in the power consumption of the bluetooth radio and baseband. the primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls. 5.2 link control layer the link control layer is part of the bl uetooth link control functions that are im plemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command controll er that takes commands from the software, and other contro llers that are activated o r configured by the command contro ller, to perform the link contro l tasks. each task perf orms a different stat e in the bluetooth link controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff ? ble adv ? ble scan/initiation 5.3 test mode support the cyw43340 fully supports bluetooth test mode as described in part i:1 of the specification of the bluetooth system version 3.0 . this includes the transmitter tests, normal and del ayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test mode, the cyw43340 also supports enhanced te sting features to simplify rf debugging and qualification and type-approval testing. these features include: fixed frequency carrier wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis
document number: 002-14943 rev. *l page 18 of 96 preliminary cyw43340 fixed frequency constant receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissi ons testing for receive mode fixed frequency constant transmission ? eight-bit fixed pattern or prbs-9 ? enables modulated signal measurements with standard rf test equipment 5.4 bluetooth power management unit the bluetooth power management unit (pmu) provides power managem ent features that can be invo ked by either software through power management registers or packet handling in the baseband co re. the power management functions provided by the cyw43340 are: rf power management host controller power management bbc power management 5.4.1 rf power management the bbc generates power-down control signals for the transmit path , receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver. the transceiver then processes the power-down functions accordingly. 5.4.2 host controller power management when running in uart mode, the cyw43340 may be configured so that dedicated signals are used for power management hand- shaking between the cyw43340 and the host. the basic power sa ving functions supported by those hand-shaking signals include the standard bluetooth defined power savi ngs modes and standby modes of operation. ta b l e 5 describes the power-control hand-shake signals used with the uart interface. table 5. power control pin description signal type description bt_dev_wake i bluetooth device wake-up: signal from the host to the cyw43340 indicati ng that the host requires attention. asserted: the bluetooth device mu st wake-up or remain awake. deasserted: the bluetooth device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. bt_host_wake o host wake up. signal from the cyw43340 to the host indicating that the cyw43340 requires attention. asserted: host device must wake-up or remain awake. deasserted: host devi ce may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. clk_req o the cyw43340 asserts clk_req when bluetooth, or wlan directs the host to turn on the reference clock. the clk_req polarity is active-high. add an external 100 k ? pull-down resistor to ensure the signal is deasserted when the cyw43340 powers up or resets when vddio is present. note: pad function control register is set to 0 for these pins.
document number: 002-14943 rev. *l page 19 of 96 preliminary cyw43340 figure 7. startup signaling sequence 5.4.3 bbc power management the ? following ? are ? low-power ? operations ? for ? the ? bbc: physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. bluetooth-specified low-power connection mode s: sniff, hold, and park. while in thes e modes, the cyw43340 runs on the low-power oscillator and wakes up after a predefined time period. a low-power shutdown feature a llows the device to be turned off while the host and any other devices in the system remain opera tional. when the cyw43340 is not needed in the system, the rf and core supplies are shut down while the i/o remains powered. this allows the cyw43340 to effectively be off while keeping the i/o pins powered so they do not draw extra curr ent from any other devices connected to the i/o. during the low-power shut-down state, provided vddio remains appli ed to the cyw43340, all outputs are tristated, and most input signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent curren t paths or create loading on any digital signals in the system and enabl es the cyw43340 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. two cyw43340 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does n ot have vddio power supplied to it: the frequency reference in put (wrf_tcxo_in) and the 32.768 khz input (lpo). when the cyw43340 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information ab out its state from the time before it was powered down. vddio lpo bt_uart_rts_n clk_req bt_gpio_1 (bt_host_wake) bt_reg_on bt_uart_cts_n host i/os }v.p? host i/os v con .p? bth ios }v.p? bth ios nco v.p? t 2 t ??o t ??o t 1 e}??w t 1 is ?z ?u fo ? ?z bth ] to ??o its ios a l? a ??? v?( ol ??o]vp ?uo aps . t 2 is ?z ?u fo ? ?z bt ] to }u?o t ]v]?o]? on v ?] bt_uart_rts_n o}x t ??o is th ?u fo ? ?z ? f c ol si pv a o (?}u th host to b p a ? a v? to ha ??o . d ? i n p oo /v i ?? that bth ic is ?? .
document number: 002-14943 rev. *l page 20 of 96 preliminary cyw43340 5.4.4 wideband speech the cyw43340 provides support for wideband speech (wbs) usin g on-chip smart audio technology. the cyw43340 can perform subband-codec (sbc), as well as msbc, encoding and decoding of li near 16 bits at 16 khz (256 kbps rate) transferred over the pc m bus. 5.4.5 packet loss concealment packet loss concealment (plc) improves ap parent audio quality for systems with margin al link performance. bluetooth messages are sent in packets. when a packe t is lost, it creates a gap in the received aud io bit-stream. packet loss can be mitigated in several ways: fill in zeros. ramp down the output audio signal toward zero (thi s is the method used in current bluetoot h headsets). repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). these techniques cause distortion and poppin g in the audio stream. the cyw43340 uses a proprietary waveform extension algorithm to provide dramatic improvem ent in the audio quality. figure 8 and figure 9 show audio waveforms with and without packet loss concealment. cypress plc/bec algori thms also support wideband speech. figure 8. cvsd decoder output waveform without plc figure 9. cvsd decoder output waveform after applying plc 5.4.6 audio rate-matching algorithms the cyw43340 has an enhanced rate-matching algorithm that uses inte rpolation algorithms to reduce audio stream jitter that may be present when the rate of audio data coming from the host is not the same as t he bluetooth audio data rates. 5.4.7 codec encoding the cyw43340 can support sbc and msbc encoding and decoding for wideband speech. 5.4.8 multiple simult aneous a2dp audio stream the cyw43340 has the ability to take a single audio stream and outp ut it to multiple bluetooth devices simultaneously. this all ows a user to share his or her music (or any audio stream) with a friend. 5.4.9 burst buffer operation the cyw43340 has a data buffer that can bu ffer data being sent over the hci and audio transports, then send the data at an incr eased rate. this mode of operation allows the ho st to sleep for the maximum amount of time, dramat ically reducing system current consumption.
document number: 002-14943 rev. *l page 21 of 96 preliminary cyw43340 5.5 adaptive frequency hopping the cyw43340 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. the link quality is determined us ing both rf and baseband signal processing to provide a more accurate frequency-hop map. 5.6 advanced bluetooth/wlan coexistence the cyw43340 includes advanced coexistence technologies that are only possible with a bluetooth/wlan integrated die solution. these coexistence technol ogies are targeted at small form-factor platforms, such as cell pho nes and media play ers, including ap pli- cations such as vowlan + sco and video-over-wlan + high fidelity bt stereo. support is provided for platforms that share a single antenna bet ween bluetooth and wlan. dual-antenna applications are also supported. the cyw43340 radio ar chitecture allows for lossless simultaneous bl uetooth and wlan reception for shared antenna applications. this is possible only via an integrated solution (shared lna and joint agc algorithm). it has superior performanc e versus implementations that need to arbitrate between bluetooth and wlan reception. the cyw43340 integrated solution enables mac-layer signaling (fi rmware) and a greater degree of sharing via an enhanced coexis- tence interface. information is exchanged between the blue tooth and wlan cores without host processor involvement. the cyw43340 also supports transmit power control on the sta t ogether with standard bluetooth tp c to limit mutual interference and receiver desensitization. preemption mec hanisms are utilized to prevent ap transm issions from colliding with bluetooth fram es. improved channel classification techniques have been implemented in bluetooth for faster and more accurate detection and elimi- nation of interferers (including non-wlan 2.4 ghz interference). the bluetooth afh classification is also enhanced by the wlan core?s channel information. 5.7 fast connection (interlaced page and inquiry scans) the cyw43340 supports page scan and inquiry scan modes that sign ificantly reduce the average in quiry response and connection times. these scanning modes are compatible with the bluetooth version 2.1 page and inquiry procedures.
document number: 002-14943 rev. *l page 22 of 96 preliminary cyw43340 6. microprocessor and memory unit for bluetooth the bluetooth microprocessor co re is based on the arm ? cortex?-m3 32-bit risc processor with embedded ice-rt debug and jtag interface units. it runs software from the link cont rol (lc) layer, up to the host controller interface (hci). the arm core is paired with a memory unit that contains 652 k b of rom memory for program storage and boot rom, 195 kb of ram for data scratchpad and patch ram code. the internal rom allo ws for flexibility during power-on reset to enable the same de vice to be used in various configurations. at power-up, the lower-lay er protocol stack is executed from the internal rom memory. external patches may be applied to the rom-based firmware to pr ovide flexibility for bug fixes or features additions. these pat ches may be downloaded from the host to the cyw43340 through the uart transports. the mechanism for downloading via uart is identical to the proven interface of the cyw4329 and cyw4330 devices. 6.1 ram, rom, and patch memory the cyw43340 bluetooth core has 195 kb of internal ram whic h is mapped between general pu rpose scratch pad memory and patch memory and 652 kb of rom used for the lower-layer protocol stack, test mode software, and boot rom. the patch memory capability enables the addition of code changes for purpose s of feature additions and bug fixes to the rom memory. 6.2 reset the cyw43340 has an integrated power-on reset circuit that resets all circuits to a known power-on state. the bt power-on reset (por) circuit is out of reset after bt_reg_on goes high. if bt_reg_on is low, then the por circuit is held in reset.
document number: 002-14943 rev. *l page 23 of 96 preliminary cyw43340 7. bluetooth periph eral transport unit 7.1 pcm interface the cyw43340 supports two independent pcm inte rfaces that share the pins with the i 2 s interfaces. the pcm interface on the cyw43340 can connect to linear pcm codec devices in master or slave mode. in master mode, the cyw43340 generates the pcm_clk and pcm_sync signals, and in slave mode, these signals are provided by another master on the pcm interface and are inputs to the cyw43340. the configuration of the pcm interface may be adjusted by the ho st through the use of vendor-specific h ci commands. 7.1.1 slot mapping the cyw43340 supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by using a time-slotting scheme where the 8 khz or 16 khz audio sam ple interval is divided into as many as 16 slots. the number of slot s is dependent on the selected interface rate of 128 khz, 512 k hz, or 1024 khz. the corresponding number of slots for these interface ra te is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. the pcm data output driver tristates its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its ou tput after the falling edge of th e pcm clock during the last bit of the slot. 7.1.2 frame synchronization the cyw43340 supports both short- and long-frame synchronization in both master and slave modes. in short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slav e looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at the next rising edge of the clock. in long-frame synchronization mode, the frame synchr onization signal is again an active-high pulse at the audio frame rate; how ever, the duration is three bit periods and the pulse starts c oincident with the first bit of the first slot. 7.1.3 data formatting the cyw43340 may be configured to generate and accept several di fferent data formats. for conv entional narrowband speech mode, the cyw43340 uses 13 of the 16 bits in each pcm frame. the location and order of th ese 13 bits can be configured to support var ious data formats on the pcm interface. the remaining three bits ar e ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. the default format is 13-bit 2? s complement data, left justified, and clocked msb first. 7.1.4 wideband speech support when the host encodes wideband speech (wbs) packets in trans parent mode, the encoded packets are transferred over the pcm bus for an esco voice connection. in this mo de, the pcm bus is typically configured in master mode for a 4 khz sync rate with 1 6- bit samples, resulting in a 64 kbps bit rate. the cyw43340 al so supports slave transparent mode using a proprietary rate-matchi ng scheme. in sbc-code mode, linear 16-bit data at 16 kh z (256 kbps rate) is transferred over the pcm bus. 7.1.5 burst pcm mode in this mode of operat ion, the pcm bus runs at a signific antly higher rate of operation to allow the host to duty cycle its ope ration and save current. in this mode of operation, the pcm bus can operate at a rate of up to 24 mhz. this mode of o peration is initiated with an hci command from the host.
document number: 002-14943 rev. *l page 24 of 96 preliminary cyw43340 7.1.6 pcm interface timing short frame sync, master mode figure 10. pcm timing diagram (short frame sync, master mode) table 6. pcm interface timing specifications (short frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_ bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7
document number: 002-14943 rev. *l page 25 of 96 preliminary cyw43340 short frame sync, slave mode figure 11. pcm timing diagram (short frame sync, slave mode) table 7. pcm interface timing specifications (short frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8
document number: 002-14943 rev. *l page 26 of 96 preliminary cyw43340 long frame sync, master mode figure 12. pcm timing diagram (long frame sync, master mode) table 8. pcm interface timing specifications (long frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-14943 rev. *l page 27 of 96 preliminary cyw43340 long frame sync, slave mode figure 13. pcm timing diagram (long frame sync, slave mode) table 9. pcm interface timing specifications (long frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-14943 rev. *l page 28 of 96 preliminary cyw43340 short frame sync, burst mode figure 14. pcm burst mode timing (receive only, short frame sync) table 10. pcm burst mode (receive only, short frame sync) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7
document number: 002-14943 rev. *l page 29 of 96 preliminary cyw43340 long frame sync, burst mode figure 15. pcm burst mode timing (receive only, long frame sync) table 11. pcm burst mode (receive only, long frame sync) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24 mhz 2 pcm bit clock low 20.8 ? ? ns 3 pcm bit clock high 20.8 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 bit ? 0 bit ? 1
document number: 002-14943 rev. *l page 30 of 96 preliminary cyw43340 7.2 uart interface the cyw43340 uses a uart for bluetooth. the uart is a standar d 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the interface features an automat ic baud rate detection capability that returns a baud rate se lection. alternatively, the baud rate may be selected through a vendor-specific uart hci command. the uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the ahb interface through either dma or th e cpu. the uart supports the bluetooth 4.0 uart hci spec ification: h4 and h5. the default baud rate is 115.2 kbaud. the uart supports the 3-wire h5 uart transport, as described in the bluetooth spec ification (?three-wire uart transport layer?) . compared to h4, the h5 uart transport reduces the number of signal lines required by eliminating the cts and rts signals. the cyw43340 uart can perform xon/xoff flow control and includes hardware support for the serial line input protocol (slip). it can also perform wake-on activi ty. for example, activity on the rx or cts inputs can wake the chip from a sleep state. normally, the uart baud rate is set by a configuration record do wnloaded after device reset, or by automatic baud rate detectio n, and the host does not need to adjust the bau d rate. support for changing the baud rate during normal hci uart operation is incl uded through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. the cyw43340 uarts operate correctly with the host uart as long as the comb ined baud rate error of the two devices is within 2% (see table 12 ). table 12. example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00
document number: 002-14943 rev. *l page 31 of 96 preliminary cyw43340 uart timing is defined in figure 16 and ta b l e 1 3 . figure 16. uart timing 7.3 i 2 s interface the cyw43340 supports an independent i 2 s digital audio port for high-fidelity bluetooth audio. the i 2 s interface supports both master and slave modes. the i 2 s signals are: i 2 s clock: i 2 s sck i 2 s word select: i 2 s ws i 2 s data out: i 2 s sdo i 2 s data in: i 2 s sdi i 2 s sck and i 2 s ws become outputs in master mode and inputs in slave mode, while i 2 s sdo always stays as an output. the channel word length is 16 bits and the data is ju stified so that the msb of the left-cha nnel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the msb of each data word is transmitted one bit clock cycle after the i 2 s ws transition, synchronous with the falling edge of bit clock. left-channel data is transmitted when i 2 s ws is low, and right-channel data is transmitted when i 2 s ws is high. data bits sent by the cyw43340 are synchr onized with the falling edge of i2s_sck and should be sampled by the receiver on the rising edge of i2s_ssck. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz. 7.3.1 i 2 s timing note: timing values specified in ta b l e 1 4 are relative to high and low threshold levels. table 13. uart timi ng specifications ref no. characteristics minimum typical maximum unit 1 delay time, uart_cts_n low to uart_txd valid ? ? 1.5 bit periods 2 setup time, uart_cts_n high before midpoint of stop bit ? ? 0.5 bit periods 3 delay time, midpoint of stop bit to uart_rts_n high ? ? 0.5 bit periods uart_cts_n uart_rxd uart_rts_n 1 2 midpoint ? of ? stop ? bit uart_txd midpoint ? of ? stop ? bit 3
document number: 002-14943 rev. *l page 32 of 96 preliminary cyw43340 note: the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fi xed mark/space ratio. for this reason, t hc and t lc are specified with respect to t. in slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the s ignal. so long as the minimum periods are greater than 0.35t r , any clock that meets the requirements can be used. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitter driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefor e, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . to allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal a nd t, always giving the receiver sufficient setup time. the data setup and hold time must not be less th an the specified receiver setup and hold time. the time periods specified in figure 17 and figure 18 on page 33 are defined by the transmitter sp eed. the receiver specifications must match transmitter performance. table 14. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min max min max min max min max clock period t t tr ???t r ???1 master mode: clock generated by transmitter or receiver high t hc 0.35t tr ???0.35t tr ???2 low t lc 0.35t tr ???0.35t tr ???2 slave mode: clock accepted by transmitter or receiver high t hc ? 0.35t tr ? ? ? 0.35t tr ??3 low t lc ? 0.35t tr ? ? ? 0.35t tr ??3 rise time t rc ? ? 0.15t tr ??? ?4 transmitter delay t dtr ???0.8t????5 hold time t htr 0???????4 receiver setup time t sr ?????0.2t r ??6 hold time t hr ?????0??6
document number: 002-14943 rev. *l page 33 of 96 preliminary cyw43340 figure 17. i 2 s transmitter timing figure 18. i 2 s receiver timing sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t rc * t hc > 0.35t t v h = ? 2.0v t htr > 0 t otr < 0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode. sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t hc > 0.35 t v h = ? 2.0v t hr > 0 t sr > 0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document number: 002-14943 rev. *l page 34 of 96 preliminary cyw43340 8. wlan global functions 8.1 wlan cpu and memory subsystem the cyw43340 includes an integrated arm cortex-m3? processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. it is intended for deeply embedd ed applications that require fast interrupt response features. the processor implements the arm architecture v7-m with support for thumb?-2 instruction set. arm cortex-m3 deliver s 30% more performance gain over arm7tdmi?. at 0.19 w/mhz, the cortex-m3 is the most power efficient general purpose microp rocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost throu gh improved memory utilization, reduced pin overhead, and reduced silicon area. arm cortex-m3 supports independent buses for code and data access (icode/dcode and system buses). arm cortex- m3 supports extensive debug features includ ing real time trace of program execution. on-chip memory for the cpu includes 512 kb sram and 640 kb rom. 8.2 one-time programmable memory various hardware configuration parameters ma y be stored in an internal 3072-bit one-time programmable (otp) memory, which is read by the system softwa re after device reset. in addition, customer-specific parameters, in cluding the system ve ndor id and t he mac address can be stored, depending on the specific board design. the initial state of all bits in an unprogr ammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with t he cypress wlan manufacturing tes t tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but onl y bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using t he appropriate editable nvram.txt file, which is provided with t he reference board design package. 8.3 gpio interface on the wlbga package, there are 8 gpio pins available on the wl an section of the cyw43340 that can be used to connect to various external devices. upon power up and reset, these pins become tristated. subsequently, they can be programmed to be either input or output pins vi a the gpio control register. 8.4 external coexistence interface an external handshake interface is available to enable signalin g between the device and an extern al co-located wireless device, such as gps, wimax, lte, or uwb, to manage wireless medium sharing for opti mum performance. the coexistence signals in figure 19 and table 15 can be enabled by software on the indicated gpio pins. figure 19. lte coexistence interface cyw4334x gpio5 wlan ercx gpio3 gpio2 lte ? chip wlan_priority lte_tx lte_rx bt
document number: 002-14943 rev. *l page 35 of 96 preliminary cyw43340 8.5 uart interface one uart interface can be enabled by software as an alternate function on pins wl_gpio4 and wl_gpio_5. provided primarily for debugging during development, this uart enables the cyw43340 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is co mpatible with the industry stan dard 16550 uart and provides a f ifo size of 64 8 in each direction. 8.6 jtag interface the cyw43340 supports the ieee 1149.1 jtag boundary scan standard for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows cy press to assist customers by us ing proprietary debug and charact er- ization test tools during board bring-up. t herefore, it is highly recommended to provid e access to the jtag pins by means of te st points or a header on all pcb designs. table 15. external coexistence interface coexistence signal gpio name type comment ercx_tx_conf/wlan_priority gpio_5 outp ut notify lte of request to sleep ercx_freq/lte_tx gpio_3 input notify wlan rx of requirement to sleep ercx_rf_active/lte_rx gpio_2 input notify wlan tx to reduce tx power
document number: 002-14943 rev. *l page 36 of 96 preliminary cyw43340 9. wlan host interfaces 9.1 sdio v2.0 the cyw43340 wlan section supports sdio version 2.0, including the following modes: it also has the ability to map the interrupt signal onto a gpio pin for applications requiring an interrupt different than what is provided by the sdio interface. the ability to force control of the gated cl ocks from within the device is also provided. sdio mode is e nabled using the strapping option pins strap_host_ifc_[3:1]. three functions are supported: function 0 standard sdio function (max blocksize/bytecount = 32b) function 1 backplane function to access the internal system- on-chip (soc) address space (max blocksize/bytecount = 64b) function 2 wlan function for efficient wlan packet transfer through dma (max blocksize/bytecount = 512b) 9.1.1 sdio pin descriptions figure 20. signal connections to sdio host (sd 4-bit mode) ds: default speed up to 25 mhz, including 1- and 4-bit modes (3.3v signaling) hs: high speed up to 50 mhz (3.3v signaling) table 16. sdio pin description sd 4-bit mode sd 1-bit mode data0 data line 0 data data line data1 data line 1 or interrupt irq interrupt data2 data line 2 or read wait rw read wait data3 data line 3 n/c not used clk clock clk clock cmd command line cmd command line sd ? host cyw43340 clk cmd dat[3:0]
document number: 002-14943 rev. *l page 37 of 96 preliminary cyw43340 figure 21. signal connections to sdio host (sd 1-bit mode) figure 22. sdio pull-up requirements sd ? host cyw43340 clk cmd data irq rw note: ? per ? section ? 6 ? of ? the ? sdio ? specification, ? 10 ? to ? 100 ? kohm ? pull-ups ? are ? required ? on ? the ? four ? data ? lines ? and ? the ? cmd ? line. ?? this ? requirement ? must ? be ? met ? during ? all ? operating ? states ? by ? using ? external ? pull-up ? resistors ? or ? properly ? programming ? internal ? sdio ? host ? pull-ups. ?? the ? cyw43340 ? does ? not ? have ? internal ? pull-ups ? on ? these ? lines. sd ? host cyw43340 clk cmd data[3:0] vddio_sd 47k (see ? note) 47k (see ? note)
document number: 002-14943 rev. *l page 38 of 96 preliminary cyw43340 9.2 hsic interface as an alternative to sdio, an hsic host interface can be enabl ed using the strapping option pins strap_host_ifc_[3:1]. hsic is a simplified derivative of the usb2.0 interface designed to replac e a standard usb phy and cable for short distances (up to 10 cm) on board point-to-point connections. using two signals, a bidirectio nal data strobe (strobe) and a bidirectional ddr data signal ( data), it provides high-speed serial 480 mbps data transfers that are 100% host driver com patible with traditional usb 2.0 cable-conne cted topologies. figure 23 shows the blocks in the hsic device core. key features of hsic include: high-speed 480 mbps data rate source-synchronous serial interface using 1.2v lvcmos signal levels no power consumed except when a data transfer is in progress maximum trace length of 10 cm. no plug-n-play support, no hot attach/removal figure 23. hsic de vice block diagram 32-bit ? on-chip ? communication ? system dma ? engines rx ? fifo tx ? fifos tx ? fifos tx ? fifos tx ? fifos tx ? fifos tx ? fifos endpoint ? management ? unit usb ? 2.0 ? protocol ? engine hsic ? phy strobe data
document number: 002-14943 rev. *l page 39 of 96 preliminary cyw43340 10. wireless lan mac and phy 10.1 mac features the cyw43340 wlan media access controller (mac) supports feat ures specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the salient features are listed below: transmission and reception of aggregated mpdus (a-mpdu) support for power management schemes, including wmm power -save, power-save multi-poll (psmp) and multiphase psmp operation support for immediate ack and block-ack policies interframe space timing support, including rifs support for rts/cts and cts-to-self fram e sequences for protecting frame exchanges back-off counters in hardware for supporting multiple priorities as specified in the wmm specification timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware hardware offload for aes-ccmp, legacy wep ciphers, wapi, and support for key management support for coexistence with bluetooth and other external radios programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support 10.1.1 mac description the cyw43340 wlan mac is designed to support high-throughput operation with low-power consumption. it does so without compromising the bluetooth coexis tence policies, thereby enabling optimal performanc e over both networks. in addition, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 24 on page 40 . the following sections provide an overview of the important modules in the mac.
document number: 002-14943 rev. *l page 40 of 96 preliminary cyw43340 figure 24. wlan mac architecture psm the programmable state machine (psm) is a micro-coded engine, whic h provides most of the low-le vel control to the hardware, to implement the ieee 802.11 sp ecification. it is a microcontroll er that is highl y optimized for flow control operations, which ar e predom- inant in implementations of communication pr otocols. the instruction set and fundamental operations are simple and general, whi ch allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratchpad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engine s, by programming internal har dware registers (ihr). these ihrs are co-located with the hardw are functions they control, and are a ccessed by the psm via the ihr bus. the psm fetches instructions from the micr ocode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations the operands are obtained from shared memory, sc ratchpad, ihrs, or instruction literals, and the results are written into the s hared memory, scratchpad, or ihrs. there are two basic branch instructions: cond itional branches and alu based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch cond ition signals are available to the psm without polling the ihrs), or on the results of alu operations. wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, and mic computation and verification . the accelerators implement t he following cipher algor ithms: legacy wep, wpa tkip, wpa2 aes- ccmp. the psm determines, based on the frame type and association info rmation, the appropriate cipher algorithm to be used. it suppli es the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames. embedded ? cpu ? interface host ? registers, ? dma ? engines tx-fifo 32 ? kb wep tkip, ? aes, ? wapi txe tx ? a-mpdu rxe pmq psm shared ? memory 6 ? kb psm ucode memory ext- ihr ifs backoff, ? btcx tsf nav ihr ? bus shm ? bus mac-phy ? interface rx-fifo 10 ? kb rx ? a-mpdu
document number: 002-14943 rev. *l page 41 of 96 preliminary cyw43340 txe the transmit engine (txe) constitutes the trans mit data path of the mac. it coordinates the dma engines to store the transmit f rames in the txfifo. it interfaces with wep module to encrypt frames , and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority re quirements. the psm uses the channel access information from the ifs module to sched ule a queue from which the next frame is transmi tted. once the frame is scheduled, the tx e hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for tr ansmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of the ma c. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interf ace and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the hea ders of the container s, and disaggregate them into component mpdus. ifs the ifs module contains the timers required to determine interfra me space timing including rifs timing. it also contains multip le backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. th e txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel ac tivity, in each slot duration, to determine whether to continu e or pause the backoff counters. when the backoff counters reach 0, the txe gets notified, so that it may commence frame transmissio n. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on polic ies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-powe r state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with it s clock turned off. a sleep timer, whose count value is initial ized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires the mac is restored to its functional state. the psm up dates the tsf timer based on the sleep duration ensuring that th e tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also maintains the target beacon trans- mission time (tbtt). the tsf time r hardware, under the control of the psm, is c apable of adopting timestamps received from beac on and probe response frames in order to ma intain synchronization with the network. the tsf module also generates trigger signals for events that ar e specified as offsets from the tsf timer, such as uplink and d ownlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav ti mer and updates the timer appropriately based on received frame s. this timing information is provided to the ifs module, which uses it as a virtual carrier-sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from /to the phy. in addition, there is an programming interface, which can be controlled either by the host or the psm to configure and control the phy.
document number: 002-14943 rev. *l page 42 of 96 preliminary cyw43340 10.2 wlan phy description the cyw43340 wlan digital phy is designed to comply with ieee 802.11a/b/g/n single-stream to provide wireless lan connectivity supporting data rates from 1 mbps to 150 mbps for low-power, high-performance handheld applications. the phy has been designed to work with interference, radio nonlinea rity, and impairments. it inco rporates efficient implementat ions of the filters, fft and viterbi decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimat ion and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide hig h throughput for ieee 802.11g/11b hybrid networks with bluetooth coexistence. it has also been designed for shared single antenna systems between wl and bt to support simultaneous rx-rx. 10.2.1 phy features supports ieee 802.11a, 11b, 11g, and 11n single-stream phy standards. ieee 802.11n single-stream operation in 20 mhz and 40 mhz channels supports optional short gi and green field modes in tx and rx. supports optional space-time block code (stb c) receive of two space-time streams. tx ldpc for improved range and power efficiency supports ieee 802.11h/k for worldwide operation. advanced algorithms for low power, enhanced sensitivity, range, and reliability algorithms to improve perform ance in presence of bluetooth simultaneous rx-rx (wl-bt) architecture automatic gain control scheme for blocking and non bl ocking application scenario for cellular applications closed loop transmit power control digital rf chip calibration algorithms to handle cmos rf chip non-idealities on-the-fly channel frequency and transmit power selection supports per packet rx antenna diversity. designed to meet fcc and other worldwide regulatory requirements.
document number: 002-14943 rev. *l page 43 of 96 preliminary cyw43340 figure 25. wlan phy block diagram one of the key features of the phy is its space-time block coding (stbc) capab ility. the stbc scheme can obtain diversity gains in a fading channel environment. on a connection with an access point that uses mu ltiple transmit antennas and supports stbc, the cyw43340 can process two space-time stre ams to improve receiver performance. figure 26 is a block diagram showing the stbc implementation in the receive path. figure 26. stbc implementation in the receive path in stbc mode, symbols are processed in pairs. equalized output symbols are linearly combined and decoded. the channel estimate is refined on every pair of symbols using the received symbols and reconstructed symbols. filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block common ? logic ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex equalizer demod ? combine demapper viterbi channel ? h symbol memory weighted ? averaging estimate channel transmitter fft ? of ? 2 ? symbols descramble ? and ? deframe h old h upd h new
document number: 002-14943 rev. *l page 44 of 96 preliminary cyw43340 11. wlan radio subsystem the cyw43340 includes an integrated dual-band wlan rf transce iver that has been optimized for use in 2.4 ghz and 5 ghz wireless lan systems. it has been designed to provide low-power, low-cost, and robust communications for applicati ons operating in the globally available 2.4 ghz unlicens ed ism or 5 ghz u-nii bands. the transmit an d receive sections include all on-chip fi ltering, mixing, and gain control functions. 11.1 receiver path the cyw43340 has a wide dynamic range, direct conversion receiver . it employs high order on-chip channel filtering to ensure re liable operation in the noisy 2.4 ghz ism band or the entire 5 ghz u- nii band. control signals are avai lable that can support the use of optional external low noise amplifiers (lna), which can increase the receive se nsitivity by several db. 11.2 transmit path baseband data is modulated and upconverted to the 2.4 ghz is m or 5-ghz u-nii bands, respectively. the cyw43340 includes an on-chip regulator which regulates vbat down to 3.3v for the cyw43340 on-chip linear power am plifiers. closed-loop output power control is provided by means of internal a-band and g-band power detectors. 11.3 calibration the cyw43340 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variation s across components. this enables the cyw43340 to be used in high-volume applications, because calibration routines are not required during manufacturing testing. these calibration routines are performed periodically in the course of normal radio oper ation. examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive perfo rmance and loft calibration for carrier leakage reduction. in addition, i/q calibration, r calibration, and vco calibration are perfor med on- chip. no per-board calibration is required in manufacturing test, which helps to minimize test time and cost during large volum e production.
document number: 002-14943 rev. *l page 45 of 96 preliminary cyw43340 12. pinout and signal descriptions 12.1 signal assignments figure 27 shows the wlbga ball map. table 17 on page 46 contains the signal description for all packages. figure 27. 141-bump cyw43340 wlbga ball map (bottom view) 12.2 signal descriptions the signal name, type, and description of each pin in the cyw43340 is listed in table 17 . the symbols shown under type indicate pin directions (i/o = bidirectional, i = input, o = output) and the internal pull-up/pull-down characteristics (pu = weak internal pull-up resistor and pd = weak internal pull -down resistor), if any. see also table 18 on page 53 for resistor strapping options. 11 10 9 8 7 6 5 4 3 2 1 a fm_lnavcovdd fm_rfin bt_vcovdd bt_lnavdd bt_rf bt_pavdd wrf_rfin_2g wrf_rfout_2g wrf_papmu_vout_ldo3p3 wrf_rfout_5g wrf_papmu_vbat_vdd5p 0a b fm_vcovss fm_lnavss bt_vcovss bt_pllvdd bt_pavss bt_ifvss wrf_pa2g_vbat_vdd3p3 wrf_cbuck_pavdd1p5 wrf_papmu_gnd b top layer metal restrict c fm_aout2 fm_pllvss bt_ifvdd bt_pllvss wrf_pa2g_vbat_gnd3p3 wrf_pa5g_vbat_gnd3p3_c3 wrf_pa5g_vbat_gnd3p3_c2 wrf_rfin_5g c depopulated d fm_aout1 fm_pllvdd bt_i2s_ws bt_i2s_clk vssc_d6 wrf_lna_2g_gnd1p2 wrf_padrv_vbat_vdd3p3 wrf_padrv_vbat_gnd3p3 wrf_gpio_out wrf_lna_5g_g nd1p2 d e clk_req bt_dev_wake vddc_e9 bt_pcm_out bt_i2s_do wrf_rx_gnd1p2 wrf_tx_gnd1p2 wrf_vco_gnd1p2 e f lpo_in bt_host_wake bt_pcm_in bt_pcm_clk bt_pcm_sync wrf_afe_gnd1p2 wrf_buck_vdd1p5 wl_gpio_1 wrf_synth_vdd1p2 wrf_xtal_cab_vdd1p2 f g bt_uart_cts_n bt_uart_txd nc_g9 rf_sw_ctrl_3 vssc_g7 rf_sw_ctrl_2 wl_gpio_6 wl_gpio_2 wl_gpio_0 wrf_ synth_gnd1p2 wrf_xtal_cab_xop g h bt_uart_rts_n bt_uart_rxd vddio_h9 rf_sw_ctrl_4 vddc_h7 rf_sw_ctrl_1 wl_gpio_5 wl_gpio_3 wrf_tcxo_vdd1p8 wrf_xtal_cab_gnd1p2 wrf_xtal_ca b_xon h j nc_j11 vss_j10 nc_j9 vss_j8 wl_gpio_4 vddio_rf wl_gpio_12 vddio_j4 wrf_tcxo_ckin2v bt_reg_on wl_reg_on j k vss_k11 vss_k10 nc_k9 vss_k8 nc_k7 sdio_data_2 sdio_data_3 rrefhsic hsic_data vddc_k1 k l vss_l11 vss_l10 vss_l9 vss_l8 nc_l7 rf_sw_ctrl_0 sdio_data_0 sdio_data_1 hsic_dvdd1p2_out hsic_strobe hsic_agnd12pll l m vss_m11 vss_m10 vss_m9 vss_m8 nc_m7 sdio_clk sdio_cmd jtag_sel vssc_m2 pmu_avss m n vss_n11 vss_n10 vss_n9 vss_n8 vss_n7 vssc_n6 vout_2p5 vout_cldo sr_vddbata5v sr_vlx n p vss_p11 vss_p10 vss_p9 vss_p8 vss_p7 vss_p6 vddc_p5 vout_lnldo ldo_vdd1p5 sr_vddbatp5v sr_pvss p 11 10 9 8 7 6 5 4 3 2 1
document number: 002-14943 rev. *l page 46 of 96 preliminary cyw43340 table 17. wlbga signal descriptions wlbga ball signal name type description wlan rf signal interface a5 wrf_rfin_2g i 2.4g rf input c1 wrf_rfin_5g i 5g rf input a4 wrf_rfout_2g o 2.4g rf output a2 wrf_rfout_5g o 5g rf output d2 wrf_gpio_out i/o ? rf control signals l6 rf_sw_ctrl_0 o rf switch enable h6 rf_sw_ctrl_1 o rf switch enable g6 rf_sw_ctrl_2 o rf switch enable g8 rf_sw_ctrl_3 o rf switch enable h8 rf_sw_ctrl_4 o rf switch enable sdio bus interface m6 sdio_clk i sdio clock input m5 sdio_cmd i/o sdio command line l5 sdio_data_0 i/o sdio data line 0 l4 sdio_data_1 i/o sdio data line 1. also used as a strapping option (see table 18 on page 53 ). k5 sdio_data_2 i/o sdio data line 2. also used as a strapping option (see table 18 on page 53 ). k4 sdio_data_3 i/o sdio data line 3 note: per section 6 of the sdio specific ation, 10 to 100 kohm pull-ups are required on the four data lines and the cmd line. this requirement must be met during all operating states by using external pull-up resistors or properly programming internal sdio host pull-ups. jtag interface m4 jtag_sel i/o jtag select: connect this pin high (vddio) in order to use gpio_2 through gpio_5 and gpio_12 as jtag signals. otherwise, if this pin is left as a no_connect, its internal pull-down selects the default mode that allows gpios 2, 3, 4, 5, and 12 to be used as gpios. note: see ?wlan gpio interface? on page 47 for the jtag signal pins. hsic interface l2 hsic_strobe i hsic strobe k2 hsic_data i/o hsic data k3 rrefhsic i hsic reference resist or input. if hsic is used, connect this pin to ground via a 51 ? 5% resistor.
document number: 002-14943 rev. *l page 47 of 96 preliminary cyw43340 wlan gpio interface g3 wl_gpio_0 i/o this pin can be programmed by software to be a gpio. f3 wl_gpio_1 i/o this pin can be programmed by software to be a gpio or an ap_ready or hsic_host_ready input from the host indicating that it is awake. g4 wl_gpio_2 i/o this pin can be programmed by software to be a gpio, the jtag tck or an hsic_ready output to the host, indica ting that the device is ready to respond with a connect when it sees idle on the hsic bus. h4 wl_gpio_3 i/o this pin can be programmed by software to be a gpio or the jtag tms signal. j7 wl_gpio_4 i/o this pin can be programmed by software to be a gpio, the jtag tdi signal, the uart rx signal, or as the wlan_host_wake output indicating that host wake-up should be performed. h5 wl_gpio_5 i/o this pin can be programmed by software to be a gpio, the jtag tdo signal or the uart tx signal. g5 wl_gpio_6 i/o gpio pin. note: some gpios are also used as strapping options (see table 18 on page 53 ). j5 wl_gpio_12 i/o this pin can be programmed by software to be a gpio or the jtag trst_l signal. gpio12 has an internal pull-down by default if jtag_sel is low. when jtag_sel is high, gpio12 is used as jtag_trst_l and is pulled up. this pin is also used as wlan_dev_wake, an out-of- band wake-up signal when the host wants to wake wlan from the deep sleep mode. note: some gpios are also used as strapping options (see table 18 on page 53 ). table 17. wlbga signal descriptions (cont.) wlbga ball signal name type description
document number: 002-14943 rev. *l page 48 of 96 preliminary cyw43340 clocks h1 wrf_xtal_cab_xon o xtal oscillator output g1 wrf_xtal_cab_xop i xtal oscillator input j3 wrf_tcxo_ckin2v i tcxo buffered input. when not using a tcxo this pin should be connected to ground. e11 clk_req o external system clock request?used when the system clock is not provided by a dedicated crystal (for example, when a shared tcxo is used). asserted to indica te to the host that the clock is required. shared by bt, and wlan. can also be programmed as the bt_i2s_di input pin if clk_req functionality is not required. f11 lpo_in i external sleep clock input (32.768 khz) bluetooth/fm receiver a7 bt_rf i/o bluetooth transceiver rf antenna port d11 fm_aout1 o fm analog output 1 c11 fm_aout2 o fm analog output 2 a10 fm_rfin i fm radio antenna port bluetooth pcm f8 bt_pcm_clk i/o pcm clock; can be master (output) or slave (input) f9 bt_pcm_in i pcm data input sensing e8 bt_pcm_out o pcm data output f7 bt_pcm_sync i/o pcm sync; can be master (output) or slave (input) table 17. wlbga signal descriptions (cont.) wlbga ball signal name type description
document number: 002-14943 rev. *l page 49 of 96 preliminary cyw43340 bluetooth uart and wake g11 bt_uart_cts_n i uart clear-to-send. active-low clear-to-send signal for the hci uart interface. h11 bt_uart_rts_n o uart request-to-send. active-low request-to- send signal for the hci uart interface. h10 bt_uart_rxd i uart serial input. serial data input for the hci uart interface. g10 bt_uart_txd o uart serial output. serial data output for the hci uart interface. e10 bt_dev_wake i/o dev_wake or general-purpose i/o signal f10 bt_host_wake i/o host_wake or general-purpose i/o signal note: by default, the blueto oth bt wake signals provide gpio/wake functi onality, and the uart pins provide uart functionality. through software configuration, the pcm interface can also be routed over the bt_wake/uart signals as follows: pcm_clk on the uart_rts_n pin pcm_out on the uart_cts_n pin pcm_sync on the bt_host_wake pin pcm_in on the bt_dev_wake pin in this case, the bt hci transport included sleep signaling will operate using uart_rxd and uart_txd; that is, using a 3-wire uart transport. bluetooth/fm i 2 s d7 bt_i2s_clk i/o i 2 s clock; can be master (o utput) or slave (input) e7 bt_i2s_do i/o i 2 s data output d8 bt_i2s_ws i/o i 2 s ws; can be master (output) or slave (input) miscellaneous j1 wl_reg_on i used by pmu to power up or power down the internal cyw43340 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. j2 bt_reg_on i used by pmu to power up or power down the internal cyw43340 regulators used by the bluetooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. table 17. wlbga signal descriptions (cont.) wlbga ball signal name type description
document number: 002-14943 rev. *l page 50 of 96 preliminary cyw43340 integrated voltage regulators n2 sr_vddbata5v i quiet vbat p2 sr_vddbatp5v i power vbat n1 sr_vlx o cbuck switching regulator output. see table 35 on page 77 for details of the inductor and capacitor required on this output. p3 ldo_vdd1p5 i input for the lnld o, cldo, and hsic ldos. it is also the voltage feedback pin for the cbuck regulator. p4 vout_lnldo o output of low-noise lnldo n3 vout_cldo o output of core ldo bluetooth power supplies a6 bt_pavdd i bluetooth pa power supply a8 bt_lnavdd i bluetooth lna power supply c8 bt_ifvdd i bluetooth if block power supply b8 bt_pllvdd i bluetooth rf pll power supply a9 bt_vcovdd i bluetooth rf power supply fm receiver power supplies d10 fm_pllvdd i fm pll power supply a11 fm_lnavcovdd i fm vco and receiver power supply pin wlan power supplies f4 wrf_buck_vdd1p5 i internal ldo supply from cbuck for vco, afe, tx, and rx b3 wrf_cbuck_pavdd1p5 i no_connect b5 wrf_pa2g_vbat_vdd3p3 i 2g pa 3.3v supply d4 wrf_padrv_vbat_vdd3p3 i 3.3v supply for a/g band pad a1 wrf_papmu_vbat_vdd5p0 i papmu vbat power supply a3 wrf_papmu_vout_ldo3p3 o papm u 3.3v ldo output voltage f2 wrf_synth_vdd1p2 i synth vdd 1.2v input h3 wrf_tcxo_vdd1p8 i supply to the wrf_tcxo_ckin input buffer. when not using a tcxo, this pin should be connected to ground. f1 wrf_xtal_cab_vdd1p2 i xtal oscillator supply table 17. wlbga signal descriptions (cont.) wlbga ball signal name type description
document number: 002-14943 rev. *l page 51 of 96 preliminary cyw43340 miscellaneous power supplies l3 hsic_dvdd1p2_out o 1.2v supply for hsic interface. this pin can be no_connect when hsic is not used. e9 vddc_e9 i core supply for wlan and bt. h7 vddc_h7 i k1 vddc_k1 i p5 vddc_p5 i h9 vddio_h9 i i/o supply (1.8?3.3v). for the wlbga package, this is the supply for both sdio and other i/o pads. j4 vddio_j4 i j6 vddio_rf i i/o supply for rf switch control pads (3.3v) n4 vout_2p5 o 2.5v ldo output ground b7 bt_pavss i bluetooth pa ground b6 bt_ifvss i 1.2v bluetooth if block ground c7 bt_pllvss i bluetooth rf pll ground b9 bt_vcovss i 1.2v bluetooth rf ground b11 fm_vcovss i fm vco ground b10 fm_lnavss i fm receiver ground c9 fm_pllvss i fm pll ground l1 hsic_agnd12pll i hsic pll ground m1 pmu_avss i quiet ground p1 sr_pvss i power ground d6 vssc_d6 i core ground for wlan and bt g7 vssc_g7 i m2 vssc_m2 i n6 vssc_n6 i g2 wrf_synth_gnd1p2 i synth ground f5 wrf_afe_gnd1p2 i afe ground d5 wrf_lna_2g_gnd1p2 i 2 ghz internal lna ground d1 wrf_lna_5g_gnd1p2 i 5 ghz internal lna ground c4 wrf_pa2g_vbat_gnd3p3 i 2.4 ghz pa ground c2 wrf_pa5g_vbat_gnd3p3_c2 i 5 ghz pa ground c3 wrf_pa5g_vbat_gnd3p3_c3 b1 wrf_papmu_gnd i pmu ground d3 wrf_padrv_vbat_gnd3p3 i pa driver ground e5 wrf_rx_gnd1p2 i rx ground e4 wrf_tx_gnd1p2 i tx ground e1 wrf_vco_gnd1p2 i vco/logen ground h2 wrf_xtal_cab_gnd1p2 i xtal ground j8 vss_j8 i ground j10 vss_j10 i ground table 17. wlbga signal descriptions (cont.) wlbga ball signal name type description
document number: 002-14943 rev. *l page 52 of 96 preliminary cyw43340 k8 vss_k8 i ground k10 vss_k10 i ground k11 vss_k11 i ground l8 vss_l8 i ground l9 vss_l9 i ground l10 vss_l10 i ground l11 vss_l11 i ground m8 vss_m8 i ground m9 vss_m9 i ground m10 vss_m10 i ground m11 vss_m11 i ground n7 vss_n7 i ground n8 vss_n8 i ground n9 vss_n9 i ground n10 vss_n10 i ground n11 vss_n11 i ground p6 vss_p6 i ground p7 vss_p7 i ground p8 vss_p8 i ground p9 vss_p9 i ground p10 vss_p10 i ground p11 vss_p11 i ground no connect g9 nc_g9 ? no connect j9 nc_j9 ? j11 nc_j11 ? k7 nc_k7 ? k9 nc_k9 ? l7 nc_l7 ? m7 nc_m7 ? table 17. wlbga signal descriptions (cont.) wlbga ball signal name type description
document number: 002-14943 rev. *l page 53 of 96 preliminary cyw43340 12.2.1 wlan gpio signals and strapping options the pins listed in table 18 on page 53 are sampled at power-on reset (por) to det ermine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each strapping option pin has an internal pull-up (pu) or pull -down (pd) resistor that determines the default mode. to change the mode, connect an external pu re sistor to vddio or a pd resistor to gnd , using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 18. wlan gpio functions and strapping options (advance information) pin name wlbga pin # default function description sdio_data_1 f9 0 strap_host_ifc_1 the three stra p pins strap_host_ifc _[3:1] select the host interface a to enable: 0xx: sdio 10x: xx 110: normal hsic 111: bootloader-less hsic a.the ? unused ? host ? interface ? is ? tristated. ? however, ? the ? sdio ? lines ? have ? internal ? pulls ? activated ? when ? in ? hsic ? mode ? (see ? table 20: ?i/o ? states,? ? on ? page 54 ). there ? are ? no ? bus-keepers ? on ? the ? hsic ? interface ? when ? it ? is ? not ? in ? use. sdio_data_2 g8 0 strap_host_ifc_2 1: select sdio mode gpio_6/ mode_sel j6 0 strap_host_ifc_3 0: select sdio mode 1: select hsic mode jtag_sel m4 n/a jtag select jtag select: connect this pin high (vddio) in order to use gpio_2 through gpio_5 and gpio_12 as jtag signals. otherwise, if this pin is left as a no_connect, its internal pull-down selects the default mode that allows gp ios 2, 3, 4, 5, and 12 to be used as gpios. note: see ?wlan gpio interface? on page 47 for the jtag signal pins.
document number: 002-14943 rev. *l page 54 of 96 preliminary cyw43340 12.2.2 cis select options cis select options are defined in ta b l e 1 9 . 12.3 i/o states the following notations are used in table 20 : i: input signal o: output signal i/o: input/output signal pu = pulled up pd = pulled down nopull = neither pulled up nor pulled down table 19. cis select otpenabled cis source otp state chipid source 0 default off default 1 otp if programmed, else default on otp if programmed, else default table 20. i/o states name i/o keeper active mode low power state/ sleep (all power present) power-down (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on=1; wl_reg_on=1) (wl_reg_on=1 and bt_reg_on=0) and vddios are present (wl_reg_on=0 and bt_reg_on=1) and vddios are present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? ? bt_reg_on i n input; pd (pull down can be disabled) input; pd (pull down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? ? clk_req i/o y open drain or push-pull (programmable). active high. open drain or push-pull (programmable). active high pd open drain. active high. open drain. active high. ?bt_vddo bt_host_wak e i/o y i/o; pu, pd, nopull (programmable) i/o; pu, pd, nopull (programmable) high-z, nopull input, pd input, pd ? bt_vddo bt_dev_wake i/o y i/o; pu, pd, nopull (programmable) input; pu, pd, nopull (programmable) high-z, nopull input, pd input, pd ? bt_vddo bt_uart_cts i y input; nopull input; nopull high-z, nopull input; pu input; pu ? bt_vddo bt_uart_rts o y output; nopull output; nopull high-z, nopull input; pu input; pu ? bt_vddo bt_uart_rxd i y input; pu input; nopull high-z, nopull input; pu input; pu ? bt_vddo bt_uart_txd o y output; nopull output; nopull high-z, nopull input; pu input; pu ? bt_vddo
document number: 002-14943 rev. *l page 55 of 96 preliminary cyw43340 sdio_data_0 i/o n hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> nopull; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull ? wl_vddi o sdio_data_1 i/o n hsic mode -> pd; sdio mode -> nopull hsic mode -> pd; sdio mode -> nopull hsic mode -> nopull; sdio mode -> nopull hsic mode -> pd; sdio mode -> pd hsic mode -> pd; sdio mode -> nopull ? wl_vddi o sdio_data_2 i/o n hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> nopull; sdio mode -> nopull hsic mode -> pu; sdio mode -> pd hsic mode -> pu; sdio mode -> nopull ? wl_vddi o sdio_data_3 i/o n hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> nopull; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull ? wl_vddi o sdio_cmd i/o n hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> nopull; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull hsic mode -> pu; sdio mode -> nopull ? wl_vddi o sdio_clk i n hsic mode -> pd; sdio mode -> nopull hsic mode -> pd; sdio mode -> nopull hsic mode -> nopull; sdio mode -> nopull hsic mode -> pd; sdio mode -> nopull hsic mode -> pd; sdio mode -> nopull ? wl_vddi o bt_pcm_clk i/o y input; nopull (note 4) input; nopull (note 4) high-z, nopull input, pd input, pd ? bt_vddo bt_pcm_in i/o y input; nopull (note 4) input; nopull (note 4) high-z, nopull input, pd input, pd ? bt_vddo bt_pcm_out i/o y input; nopull (note 4) input; nopull (note 4) high-z, nopull input, pd input, pd ? bt_vddo bt_pcm_sync i/o y input; nopull (note 4) input; nopull (note 4) high-z, nopull input, pd input, pd ? bt_vddo bt_i2s_ws i/o y input; nopull (note 5) input; nopull (note 5) high-z, nopull input, pd input, pd ? bt_vddo bt_i2s_clk i/o y input; nopull (note 5) input; nopull (note 5) high-z, nopull input, pd input, pd ? bt_vddo bt_i2s_do i/o y input; nopull (note 5) input; nopull (note 5) high-z, nopull input, pd input, pd ? bt_vddo jtag_sel i y pd pd pd pd pd pd wl_vddi o gpio_0 i/o y pd pd nopull pd pd pd wl_vddi o gpio_1 i/o y nopull nopull nopul l nopull nopull nopull wl_vddi o gpio_2 i/o y pu pu nopull pu pu pu wl_vddi o gpio_3 i/o y jtag_sel = 1 pu; jtag_sel=0 pd jtag_sel=1 pu; jtag_sel=0 pd nopull jtag_sel=1 pu; jtag_sel=0 pd jtag_sel=1 pu; jtag_sel=0 pd jtag_sel = 1 pu; jtag_sel = 0 pd wl_vddi o table 20. i/o states (cont.) name i/o keeper active mode low power state/ sleep (all power present) power-down (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on=1; wl_reg_on=1) (wl_reg_on=1 and bt_reg_on=0) and vddios are present (wl_reg_on=0 and bt_reg_on=1) and vddios are present power rail
document number: 002-14943 rev. *l page 56 of 96 preliminary cyw43340 gpio_4 i/o y jtag_sel=1 pu; jtag_sel=0 pd jtag_sel=1 pu; jtag_sel=0 pd nopull jtag_sel=1 pu; jtag_sel=0 pd jtag_sel=1 pu; jtag_sel=0 pd jtag_sel = 1 pu; jtag_sel = 0 pd wl_vddi o gpio_5 i/o y nopull nopull nopul l nopull nopull nopull wl_vddi o gpio_6 i/o y pd pd nopull pd pd pd wl_vddi o gpio_12 i/o y jtag_sel=1 pu; jtag_sel=0 pd jtag_sel=1 pu; jtag_sel=0 pd nopull jtag_sel=1 pu; jtag_sel=0 pd jtag_sel=1 pu; jtag_sel=0 pd pu wl_vddi o 1. keeper column: n=pad has no keeper. y=pad has a keeper. keeper is always active e xcept in powe r-down state. 2. if there is no keeper, and it is an input and there is nopull, th en the pad should be driven to prevent leakage due to floating pad (e.g., sdio_clk). 3. in the power-down state (xx_reg_on=0 ): high-z; nopull => the pad is disabled because power is not supplied. 4. depending on whether the pcm interface is en abled and the configuration of pcm is in ma ster or slave mode, it can be either out put or input. 5. depending on whether the i 2 s interface is enabled and the configuration of i 2 s is in master or slave mode, it can be either output or input. 6. gpio_6 is input-only during the low-power and deep-sleep modes. 7. gpio_0 through gpio_5 and gpio_12 can be configured to operate as inputs or outputs in deep-sleep mode before entering the mode . 8. the gpio pull states for the active and low -power states are hardware defaults. they can all be subsequently programmed as pull -ups or pull-downs. 9. regarding gpio pins, the following are the pull-up and pull-down values for both 3.3v and 1.8v vddio: minimum ? (k ? ) typical ? (k ? ) maximum ? (k ? ) 3.3v ? vddio, ? pull-downs: ? 51.5 44.5 38 3.3v ? vddio, ? pull-ups: ? 37.4 39.5 44.5 1.8v ? vddio, ? pull-downs: ? 64 83 116 1.8v ? vddio, ? pull-ups: ? 65 86 118 table 20. i/o states (cont.) name i/o keeper active mode low power state/ sleep (all power present) power-down (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on=1; wl_reg_on=1) (wl_reg_on=1 and bt_reg_on=0) and vddios are present (wl_reg_on=0 and bt_reg_on=1) and vddios are present power rail
document number: 002-14943 rev. *l page 57 of 96 preliminary cyw43340 13. dc characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 13.1 absolute maximum ratings caution! the absolute maximum ratings in table 21 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. fu nctional operation is not guara nteed under these conditions. operation at absolute maximum conditions for ex tended periods can advers ely affect long-term re liability of the device. 13.2 environmental ratings the environmental ratings are shown in ta b l e 2 2 . table 21. absolute maximum ratings rating symbol value unit dc supply for vbat and pa driver supply: vbat ?0.5 to +6.0 v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo1 ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v wrf_tcxo_vdd ? ?0.5 to 3.63 v maximum undershoot voltage for i/o v undershoot ?0.5 v maximum overshoot voltage for i/o v overshoot 0.5 v maximum junction temperature t j 125 c table 22. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85 c functional operation a a.functionality ? is ? guaranteed ? but ? specifications ? require ? derating ? at ? extreme ? temperatures; ? see ? the ? specification ? tables ? for ? details. ? storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation
document number: 002-14943 rev. *l page 58 of 96 preliminary cyw43340 13.3 electrostatic discharge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding strap s to discharge static electricity is required when handling these devices. always store unused material in its antistatic packagi ng. 13.4 recommended operating conditions and dc characteristics caution! functional operation is not guarant eed outside of the limits shown in ta b l e 2 4 and operation outside these limits for extended periods can adversely af fect long-term reliability of the device. table 23. esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 2000 v machine model (mm) esd_hand_mm machine model contact 100 v cdm esd_hand_cdm charged device model contact discharge per jedec eia/ jesd22-c101 500 v table 24. recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage for vbat vbat 2.9 a ?4.8 b v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for tcxo input buffer wrf_tcxo_vdd 1.62 1.8 1.98 v dc supply voltage for digital i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v internal por threshold vth_por 0.4 ? 0.7 v sdio interface i/o pins for vddio_sd = 1.8v: input high voltage vih 1.27 ? ? v input low voltage vil ? ? 0.58 v output high voltage @ 2 ma voh 1.40 ? ? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio_sd = 3.3v: input high voltage vih 0.625 vddio ? ? v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ? - v output low voltage @ 2 ma vol ? ? 0.125 vddio v
document number: 002-14943 rev. *l page 59 of 96 preliminary cyw43340 other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ? v input low voltage vil - ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio = 3.3v: input high voltage vih 2.00 ? ? v input low voltage vil ? ? 0.80 v output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v rf switch control output pins c for vddio_rf = 3.3v: output high voltage voh vddio ? 0.4 ? ? v output low voltage vol ? ? 0.40 v input capacitance c in ??5pf a. ? the ? cyw43340 ? is ? functional ? across ? this ? range ? of ? voltages. ? optimal ? rf ? performance ? specified ? in ? the ? data ? sheet, ? however, ? is ? guaranteed ? only ? for ? 3.0v ? < ? vbat < ? 4.8v. ? b. ? the ? maximum ? continuous ? voltage ? is ? 4.8v. ? voltages ? up ? to ? 5.5v ? for ? up ? to ? 10 ? seconds, ? cumulative ? duration, ? over ? the ? lifetime ? of ? the ? device ? are ? allowed. ? volt- ages ? as ? high ? as ? 5.0v ? for ? up ? to ? 250 ? seconds, ? cumulative ? duration, ? over ? the ? lifetime ? of ? the ? device ? are ? allowed. c. ? programmable ? 2 ? ma ? to ? 16 ? ma ? drive ? strength. ? default ? is ? 10 ? ma. table 24. recommended operating conditions and dc characteristics (cont.) parameter symbol value unit minimum typical maximum
document number: 002-14943 rev. *l page 60 of 96 preliminary cyw43340 14. bluetooth rf specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, limit values app ly for the conditions specified in table 22: ?environmental ratings,? on page 57 and table 24: ?recommended operating conditions and dc characteristics,? on page 58 . typical values apply for the following condi- tions: vbat = 3.6v ambient temperature +25c figure 28. rf port location for bluetooth testing note: all bluetooth specifications are measured at the chip port unle ss otherwise specified. cyw43340 antenna ? port 2.4 ? ghz ? wlan + bt ? tx/rx chip port filter
document number: 002-14943 rev. *l page 61 of 96 preliminary cyw43340 table 25. bluetooth receiver rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the chip port output unless otherwise specified. general frequency range ? 2402 ? 2480 mhz rx sensitivity gfsk, 0.1% ber, 1 mbps ? ?92.5 ? dbm ? /4?dqpsk, 0.01% ber, 2 mbps ??94.5?dbm 8?dpsk, 0.01% ber, 3 mbps ? ?88.5 ? dbm input ip3 ? ?16 ? ? dbm maximum input at antenna ? ? ? ?20 dbm interference performance a c/i co-channel gfsk, 0.1% ber ? ? 11 db c/i 1-mhz adjacent channel gfsk, 0.1% ber ? ? 0.0 db c/i 2-mhz adjacent channel gfsk, 0.1% ber ? ? ?30 db c/i ? 3-mhz adjacent channel gfsk, 0.1% ber ? ? ?40 db c/i image channel gfsk, 0.1% ber ? ? ?9 db c/i 1-mhz adjacent to image channel gfsk, 0.1% ber ? ? ?20 db c/i co-channel ? /4?dqpsk, 0.1% ber ? ? 13 db c/i 1-mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ? 0.0 db c/i 2-mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ? ?30 db c/i ? 3-mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ? ?40 db c/i image channel ? /4?dqpsk, 0.1% ber ? ? ?7 db c/i 1-mhz adjacent to image channel ? /4?dqpsk, 0.1% ber ? ? ?20 db c/i co-channel 8?dpsk, 0.1% ber ? ? 21 db c/i 1 mhz adjacent channel 8?dpsk, 0.1% ber ? ? 5.0 db c/i 2 mhz adjacent channel 8?dpsk, 0.1% ber ? ? ?25 db c/i ? 3-mhz adjacent channel 8?dpsk, 0.1% ber ? ? ?33 db c/i image channel 8?dpsk, 0.1% ber ? ? 0.0 db c/i 1-mhz adjacent to image channel 8?dpsk, 0.1% ber ? ? ?13 db out-of-band blocking performance (cw) 30?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm out-of-band blocking performance, modulated interferer (lte) gfsk (1 mbps) 2310mhz lte band40 tdd 20m bw ? ?20 ? dbm 2330mhz lte band40 tdd 20m bw ? ?21 ? dbm 2350mhz lte band40 tdd 20m bw ? ?22 ? dbm 2370mhz lte band40 tdd 20m bw ? ?23 ? dbm
document number: 002-14943 rev. *l page 62 of 96 preliminary cyw43340 2510mhz lte band7 fdd 20m bw ? ?26 ? dbm 2530mhz lte band7 fdd 20m bw ? ?25 ? dbm 2550mhz lte band7 fdd 20m bw ? ?25 ? dbm 2570mhz lte band7 fdd 20m bw ? ?24 ? dbm ? /4 dpsk (2 mbps) 2310mhz lte band40 tdd 20m bw ? ?20 ? dbm 2330mhz lte band40 tdd 20m bw ? ?20 ? dbm 2350mhz lte band40 tdd 20m bw ? ?22 ? dbm 2370mhz lte band40 tdd 20m bw ? ?23 ? dbm 2510mhz lte band7 fdd 20m bw ? ?26 ? dbm 2530mhz lte band7 fdd 20m bw ? ?25 ? dbm 2550mhz lte band7 fdd 20m bw ? ?25 ? dbm 2570mhz lte band7 fdd 20m bw ? ?24 ? dbm 8dpsk (3 mbps) 2310mhz lte band40 tdd 20m bw ? ?21 ? dbm 2330mhz lte band40 tdd 20m bw ? ?21 ? dbm 2350mhz lte band40 tdd 20m bw ? ?23 ? dbm 2370mhz lte band40 tdd 20m bw ? ?24 ? dbm 2510mhz lte band7 fdd 20m bw ? ?26 ? dbm 2530mhz lte band7 fdd 20m bw ? ?25 ? dbm 2550mhz lte band7 fdd 20m bw ? ?25 ? dbm 2570mhz lte band7 fdd 20m bw ? ?24 ? dbm out-of-band blocking performance, modulated interferer (non-lte) gfsk (1 mbps) a 698?716 mhz wcdma ? ?13 ? dbm 776?849 mhz wcdma ? ?13 ? dbm 824?849 mhz gsm850 ? ?13 ? dbm 824?849 mhz wcdma ? ?13 ? dbm 880?915 mhz e-gsm ? ?13 ? dbm 880?915 mhz wcdma ? ?13 ? dbm 1710?1785 mhz gsm1800 ? ?19 ? dbm 1710?1785 mhz wcdma ? ?19 ? dbm 1850?1910 mhz gsm1900 ? ?20 ? dbm 1850?1910 mhz wcdma ? ?20 ? dbm 1880?1920 mhz td-scdma ? ?20 ? dbm 1920?1980 mhz wcdma ? ?20 ? dbm 2010?2025 mhz td?scdma ? ?21 ? dbm 2500?2570 mhz wcdma ? ?23 ? dbm table 25. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-14943 rev. *l page 63 of 96 preliminary cyw43340 ? /4 dpsk (2 mbps) a 698?716 mhz wcdma ? ?11 ? dbm 776?794 mhz wcdma ? ?11 ? dbm 824?849 mhz gsm850 ? ?12 ? dbm 824?849 mhz wcdma ? ?12 ? dbm 880?915 mhz e-gsm ? ?12 ? dbm 880?915 mhz wcdma ? ?12 ? dbm 1710?1785 mhz gsm1800 ? ?17 ? dbm 1710?1785 mhz wcdma ? ?17 ? dbm 1850?1910 mhz gsm1900 ? ?19 ? dbm 1850?1910 mhz wcdma ? ?18 ? dbm 1880?1920 mhz td-scdma ? ?19 ? dbm 1920?1980 mhz wcdma ? ?19 ? dbm 2010?2025 mhz td-scdma ? ?21 ? dbm 2500?2570 mhz wcdma ? ?23 ? dbm 8dpsk (3 mbps) a 698?716 mhz wcdma ? ?13 ? dbm 776?794 mhz wcdma ? ?12 ? dbm 824?849 mhz gsm850 ? ?13 ? dbm 824?849 mhz wcdma ? ?13 ? dbm 880?915 mhz e-gsm ? ?13 ? dbm 880?915 mhz wcdma ? ?13 ? dbm 1710?1785 mhz gsm1800 ? ?18 ? dbm 1710?1785 mhz wcdma ? ?18 ? dbm 1850?1910 mhz gsm1900 ? ?20 ? dbm 1850?1910 mhz wcdma ? ?19 ? dbm 1880?1920 mhz td-scdma ? ?20 ? dbm 1920?1980 mhz wcdma ? ?20 ? dbm 2010?2025 mhz td-scdma ? ?21 ? dbm 2500?2570 mhz wcdma ? ?24 ? dbm rx lo leakage 2.4 ghz band ? ? ?90.0 ?80.0 dbm spurious emissions 30 mhz?1 ghz ? ?95 ?62 dbm 1?12.75 ghz ? ?70 ?47 dbm 869?894 mhz ? ?147 ? dbm/hz 925?960 mhz ? ?147 ? dbm/hz 1805?1880 mhz ? ?147 ? dbm/hz 1930?1990 mhz ? ?147 ? dbm/hz table 25. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-14943 rev. *l page 64 of 96 preliminary cyw43340 2110?2170 mhz ? ?147 ? dbm/hz a. ? the ? bluetooth ? reference ? level ? for ? the ? required ? signal ? at ? the ? bluetooth ? chip ? port ? is ? 3db ? higher ? than ? the ? typical ? sensitivity ? level. table 25. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-14943 rev. *l page 65 of 96 preliminary cyw43340 table 26. bluetooth transmitter rf specifications a a. ? unless ? otherwise ? specified, ? the ? specifications ? in ? this ? table ? are ? measured ? at ? the ? chip ? output ? port, ? and ? output ? power ? specifications ? are ? with ? the ? temperature correction ? algorithm ? and ? tssi ? enabled. parameter conditions minimum typical maximum unit general frequency range 2402 ? 2480 mhz basic rate (gfsk) tx power at bluetooth ? 11.0 ? dbm qpsk tx power at bluetooth ? 8.0 ? dbm 8psk tx power at bluetooth ? 8.0 ? dbm power control step 2 4 8 db gfsk in-band spurious emissions ?20 dbc bw ? ? .93 1 mhz edr in-band spur ious emissions 1.0 mhz < |m ? n| < 1.5 mhz m ? n = the frequency range for which the spurious emission is measured relative to the transmit center frequency. ? ?38 ?26.0 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ?31 ?20.0 dbm |m ? n| ? 2.5 mhz b b. ? typically ? measured ? at ? an ? offset ? of ? 3 ? mhz. ? ?43 ?40.0 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 c,d c. ? the ? maximum ? value ? represents ? the ? value ? required ? for ? bluetooth ? qualification ? as ? defined ? in ? the ? v4.0 ? specification. ? d. ? the ? spurious ? emissions ? during ? idle ? mode ? are ? the ? same ? as ? specified ? in ? table ? 26 ? on ? page ? 65 . dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 d,e,f e. ? specified ? at ? the ? bluetooth ? antenna ? port. f. ? meets ? this ? specification ? using ? a ? front-end ? band-pass ? filter. dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm gps band spurio us emissions spurious emissions ? ? ?103 ? dbm out-of-band no ise floor g g. ? transmitted ? power ? in ? cellular ? and ? fm ? bands ? at ? the ? bluetooth ? antenna ? port. ? see ? figure ? 28 ? on ? page ? 60 ? for ? location ? of ? the ? port. ? 65?108 mhz fm rx ? ?147 ? dbm/hz 776?794 mhz cdma2000 ? ?147 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?147 ? dbm/hz 925?960 mhz e-gsm ? ?147 ? dbm/hz 1570?1580 mhz gps ? ?146 ? dbm/hz 1805?1880 mhz gsm1800 ? ?145 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?144 ? dbm/hz 2110?2170 mhz wcdma ? ?141 ? dbm/hz
document number: 002-14943 rev. *l page 66 of 96 preliminary cyw43340 table 27. local oscillator performance parameter minimum typical maximum unit lo performance lock time ? 72 ? ? s initial carrier frequency tolerance ? 25 75 khz frequency drift dh1 packet ? 8 25 khz dh3 packet ? 8 40 khz dh5 packet ? 8 40 khz drift rate ? 5 20 khz/50 s frequency deviation 00001111 sequence in payload a a. this pattern represents an average deviation in payload. 140 155 175 khz 10101010 sequence in payload b b. pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 115 140 ? khz channel spacing ? 1 ? mhz table 28. ble rf specifications parameter conditions minimum typical maximum unit frequency range ? 2402 2480 mhz rx sense a a.the ? bluetooth ? tester ? is ? set ? so ? that ? dirty ? tx ? is ? on. gfsk, 0.1% ber, 1 mbps ? ?94.5 ? dbm tx power b b.ble ? tx ? power ? can ? be ? increased ? to ? compensate ? for ? front-end ? losses ? such ? as ? bpf, ? diplexer, ? switch, ? and ? so ? forth). ? the ? output ? is ? capped ? at ? 12 ? dbm ? out. ? the ble ? tx ? power ? at ? the ? antenna ? port ? cannot ? exceed ? the ? 10 ? dbm ? specification ? limit. ??8.5?dbm mod char: delta f1 average ? 225 255 275 khz mod char: delta f2 max c c.at ? least ? 99.9% ? of ? all ? delta ? f2 ? max ? frequency ? values ? recorded ? over ? 10 ? packets ? must ? be ? greater ? than ? 185 ? khz. ?99.9??% mod char: ratio ? 0.8 0.95 ? %
document number: 002-14943 rev. *l page 67 of 96 preliminary cyw43340 15. wlan rf specifications 15.1 introduction the cyw43340 includes an integrated dual-band direct conversion radio that supports either the 2.4 ghz band or the 5 ghz band. the cyw43340 does not provide simultaneous 2.4 ghz and 5 ghz opera tion. this section describes the rf characteristics of the 2.4 ghz and 5 ghz portions of the radio. values in this data sheet are design goals and are subjec t to change based on the result s of device characterization. unless otherwise stated, lim it values apply for the conditions specified in table 22: ?environmental ratings,? on page 57 and table 24: ?recommended operating conditions and dc characteristics,? on page 58 . typical values apply for the following condi- tions: vbat = 3.6v ambient temperature +25c figure 29. wlan port locations (5 ghz) figure 30. wlan port locations (2.4 ghz) note: all wlan specifications are measured at the chip port, unless otherwise specified. cyw43340 antenna ? port 5 ? ghz ? wlan chip port fem ? or t/r ? switch cyw43340 antenna ? port 2.4 ? ghz ? wlan + bt ? tx/rx chip port filter
document number: 002-14943 rev. *l page 68 of 96 preliminary cyw43340 15.2 2.4 ghz band general rf specifications 15.3 wlan 2.4 ghz receiver performance specifications note: the specifications in table 30 are measured at the chip port, unless otherwise specified. table 29. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s power-up and power-down ramp ti me dsss/cck modulations ? ? < 2 s table 30. wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity (8% per for 1024 octet psdu) a 1 mbps dsss ? ?99 ? dbm 2 mbps dsss ? ?95 ? dbm 5.5 mbps cck ? ?93 ? dbm 11 mbps cck ? ?89 ? dbm rx sensitivity (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?92 ? dbm 9 mbps ofdm ? ?92 ? dbm 12 mbps ofdm ? ?89 ? dbm 18 mbps ofdm ? ?87 ? dbm 24 mbps ofdm ? ?84 ? dbm 36 mbps ofdm ? ?82 ? dbm 48 mbps ofdm ? ?78 ? dbm 54 mbps ofdm ? ?77 ? dbm rx sensitivity (10% per for 4096 octet psdu) a,b. defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates (gf) mcs0 ? ?92 ? dbm 13 mbps mcs 1 ? ?88 ? dbm 6.5 mbps mcs 2 ? ?86 ? dbm mcs 3 ? ?84 ? dbm mcs 4 ? ?81 ? dbm mcs 5 ? ?76 ? dbm mcs 6 ? ?75 ? dbm mcs 7 ? ?73 ? dbm
document number: 002-14943 rev. *l page 69 of 96 preliminary cyw43340 rx sensitivity (10% per for 4096 octet psdu) a,b. defined for default parameters: gf, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates (gf) mcs 0 ? ?89 ? dbm mcs 1 ? ?85 ? dbm mcs 2 ? ?83 ? dbm mcs 3 ? ?81 ? dbm mcs 4 ? ?78 ? dbm mcs 5 ? ?74 ? dbm mcs 6 ? ?71 ? dbm mcs 7 ? ?69 ? dbm rx sensitivity (10% per for 4096 octet psdu) a,c. defined for default parameters: mixed mode, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates (mixed mode) mcs0 ? ?91.0 ? dbm mcs 1 ? ?87.9 ? dbm mcs 2 ? ?85.5 ? dbm mcs 3 ? ?82.8 ? dbm mcs 4 ? ?79.9 ? dbm mcs 5 ? ?76.2 ? dbm mcs 6 ? ?74.6 ? dbm mcs 7 ? ?72.6 ? dbm rx sensitivity (10% per for 4096 octet psdu) a,b. defined for default parameters: mixed mode, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates (mixed mode) mcs 0 ? ?89.0 ? dbm mcs 1 ? ?85.4 ? dbm mcs 2 ? ?83.2 ? dbm mcs 3 ? ?80.6 ? dbm mcs 4 ? ?77.4 ? dbm mcs 5 ? ?72.3 ? dbm mcs 6 ? ?70.6 ? dbm mcs 7 ? ?69.0 ? dbm table 30. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14943 rev. *l page 70 of 96 preliminary cyw43340 blocking level for 3db rx sensi- tivity degradation (without external filtering) d 776?794 mhz cdma2000 ?12.3 ? ? dbm 824?849 mhz e cdmaone ?9.4 ? ? dbm 824?849 mhz gsm850 ?2.7 ? ? dbm 880?915 mhz e-gsm ?3.4 ? ? dbm 1710?1785 mhz gsm1800 ?9 ? ? dbm 1850?1910 mhz gsm1800 ?8.8 ? ? dbm 1850?1910 mhz cdmaone ?22.4 ? ? dbm 1850?1910 mhz wcdma ?18.6 ? ? dbm 1920?1980 mhz wcdma ?22.5 ? ? dbm 2496?2690 mhz lte + 3 db desense ?37.2 ? ? dbm 2300?2400 mhz lte + 3 db desense ?37.2 ? ? dbm 2300?2370 mhz lte + 3 db desense ?37.2 ? ? dbm 2570?2620 mhz lte + 3 db desense ?37.2 ? ? dbm 2545?2575 mhz lte + 3 db desense ?37.2 ? ? dbm in-band static cw jammer immunity (fc ? 8 mhz < fcw < + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsens + 23 db < rxlevel < max input level) ?80 ? ? dbm input in-band ip3 a maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1024 octets) ?19.5 ? ? dbm @ mcs0?7 rates (10% per, 4095 octets) ?19.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 10 mhz adjacent channel rejection- dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection- ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db table 30. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14943 rev. *l page 71 of 96 preliminary cyw43340 adjacent channel rejection mcs0?7 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs7 ?61 dbm ?2 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs5 ?63 dbm 0 ? ? db mcs4 ?67 dbm 4 ? ? db mcs3 ?71 dbm 8 ? ? db mcs2 ?74 dbm 11 ? ? db mcs1 ?76 dbm 13 ? ? db mcs0 ?79 dbm 16 ? ? db maximum receiver gain ? ? ? 105 ? db gain control step ? ? ? 3 ? db rssi accuracy f range ?98 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? , across the dynamic range 6 10 ? db receiver cascaded nf at maximum gain ? 3.5 ? a.derate ? by ? 1.5 ? db ? for ? ?30 ? c ? to ? ?10c ? and ? 55c ? to ? 85c. b.sensitivity ? degradations ? for ? alternate ? settings ? in ? mcs ? modes. ? mm: ? 0.5 ? db ? drop, ? sgi: ? 2 ? db ? drop, ? and ? stbc: ? 0.75 ? db ? drop. c.sensitivity ? degradations ? for ? alternate ? settings ? in ? mcs ? modes. ? mm: ? 0.5 ? db ? drop, ? sgi: ? 2 ? db ? drop, ? and ? stbc: ? 0.75 ? db drop. d.the ? cellular ? standard ? listed ? for ? each ? band ? indicates ? the ? type ? of ? modulation ? used ? to ? generate ? the ? interfering ? signal ? in ? that ? band ? for ? the ? purpose ? of ? this ? test. it ? is ? not ? intended ? to ? indicate ? any ? specific ? usage ? of ? each ? band ? in ? any ? specific ? country. e.the ? blocking ? levels ? are ? valid ? for ? channels ? 1 ? to ? 11. ? (for ? higher ? channels, ? the ? performance ? may ? be ? lower ? due ? to ? third ? harmonic ? signals ? (3 ? ? 824 ? mhz) ? falling within ? band.) f.the ? minimum ? and ? maximum ? values ? shown ? have ? a ? 95% ? confidence ? level. table 30. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14943 rev. *l page 72 of 96 preliminary cyw43340 15.4 wlan 2.4 ghz transmitter performance specifications note: the specifications in table 31 are measured at the chip port output, unless otherwise specified. table 31. wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and fm bands (?18 dbm at the antenna port, 90% duty cycle, ofdm) a a. ? the ? cellular ? standards ? listed ? indicate ? only ? typical ? usages ? of ? that ? band ? in ? some ? countries. ? other ? standards ? may ? also ? be ? used ? within ? those ? bands. 76?108 mhz fm rx ? ?166 ? dbm/hz 776?794 mhz cdma2000 ? ?166 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?165 ? dbm/hz 925?960 mhz e-gsm ? ?165 ? dbm/hz 1570?1580 mhz gps ? ?155 ? dbm/hz 1805?1880 mhz gsm1800 ? ?147 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?141 ? dbm/hz 2010?2170 mhz wcdma ? ?138 ? dbm/hz 2400?2483 mhz bt/wlan ? ? ? dbm/hz 2.4 ghz gps/glonass ? ?147 ? dbm/mhz 2.4 ghz 2170 mhz band ? ?131 dbm/mhz 2.4 ghz lte band 40 ? ?109 dbm/hz 2.4 ghz lte band 7 ? ?121 dbm/hz 2.4 ghz lte band 38 ? ?115 dbm/hz 2.4 ghz lte band 41 ? ?104 dbm/hz 2.4 ghz lte band xgp ? ?110 dbm/hz harmonic level (at 18 dbm with 100% duty cycle) 4.8?5.0 ghz 2nd harmonic ? ? ?48.4 dbm/1 mhz 7.2?7.5 ghz 3rd harmonic ? ? ?56.9 dbm/1 mhz tx power at chip port for highest power level setting at 25c, vbat = 3.6v, spectral mask and evm compliance b b. ? derate ? by ? 2db ? for ? ?30c ? to ? ?10c ? and ? 55c ? to ? 85c. ? 1 mbps dsss 0 dbm ? 20 ? dbm 6 mbps ?3 dbm ? 19.5 ? dbm 54 mbps ?6 dbm ? 18 ? dbm mcs7 (20 mhz) ? 16.5 ? dbm mcs7 (40 mhz) ? 16.5 ? dbm mcs7 (20 mhz, sgi) ? 16.5 ? dbm mcs7 (40 mhz, sgi) ? 16.5 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.5 ? degrees tx power control dynamic range ?30??db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss at chip port tx z o = 50 ? 46?db
document number: 002-14943 rev. *l page 73 of 96 preliminary cyw43340 15.5 wlan 5 ghz receiver performance specifications note: the specifications in table 32 are measured at the chip port input, unless otherwise specified. table 32. wlan 5 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz rx sensitivity (10% per for 1000 octet psdu) a 6 mbps ofdm ? ?90.5 ? dbm 9 mbps ofdm ? ?90.5 ? dbm 12 mbps ofdm ? ?87.5 ? dbm 18 mbps ofdm ? ?85.5 ? dbm 24 mbps ofdm ? ?82.5 ? dbm 36 mbps ofdm ? ?80.5 ? dbm 48 mbps ofdm ? ?76.5 ? dbm 54 mbps ofdm ? ?73.5 ? dbm rx sensitivity (10% per for 4096 octet psdu) a defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates (gf) mcs 0 ? ?90.5 ? dbm mcs 1 ? ?86.5 ? dbm mcs 2 ? ?84.5 ? dbm mcs 3 ? ?82.5 ? dbm mcs 4 ? ?78.5 ? dbm mcs 5 ? ?73.5 ? dbm mcs 6 ? ?71.5 ? dbm mcs 7 ? ?70.5 ? dbm rx sensitivity (10% per for 4096 octet psdu) a defined for default parameters: gf, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates (gf) mcs 0 ? ?87.5 ? dbm mcs 1 ? ?84.5 ? dbm mcs 2 ? ?81.5 ? dbm mcs 3 ? ?80.5 ? dbm mcs 4 ? ?76.5 ? dbm mcs 5 ? ?71.5 ? dbm mcs 6 ? ?69.5 ? dbm mcs 7 ? ?68.5 ? dbm rx sensitivity (10% per for 4096 octet psdu) a defined for default parameters: mixed mode, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates (mixed mode) mcs 0 ? ?89.5 ? dbm mcs 1 ? ?86.4 ? dbm mcs 2 ? ?84.0 ? dbm mcs 3 ? ?81.3 ? dbm mcs 4 ? ?78.4 ? dbm mcs 5 ? ?74.7 ? dbm mcs 6 ? ?73.1 ? dbm mcs 7 ? ?71.1 ? dbm
document number: 002-14943 rev. *l page 74 of 96 preliminary cyw43340 rx sensitivity (10% per for 4096 octet psdu) a defined for default parameters: mixed mode, 800 ns gi, and non-stbc. 40 mhz channel spacing for all mcs rates (mixed mode) mcs 0 ? ?87.5 ? dbm mcs 1 ? ?83.9 ? dbm mcs 2 ? ?81.7 ? dbm mcs 3 ? ?79.1 ? dbm mcs 4 ? ?75.9 ? dbm mcs 5 ? ?70.8 ? dbm mcs 6 ? ?69.1 ? dbm mcs 7 ? ?67.5 ? dbm blocking level for 1 db rx sensitivity degr adation (without external filtering) b 776?794 mhz cdma2000 ?21 ? ? dbm 824?849 mhz cdmaone ?20 ? ? dbm 824?849 mhz gsm850 ?12 ? ? dbm 880?915 mhz e-gsm ?12 ? ? dbm 1710?1785 mhz gsm1800 ?15 ? ? dbm 1850?1910 mhz gsm1800 ?15 ? ? dbm 1850?1910 mhz cdmaone ?20 ? ? dbm 1850?1910 mhz wcdma ?24 ? ? dbm 1920?1980 mhz wcdma ?24 ? ? dbm input in-band ip3 a maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 5.24 ghz @ 6, 9, 12 mbps ?29.5 ? ? dbm @ 18, 24, 36, 48, 54 mbps ?29.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 18 mhz adjacent channel rejection (difference between interfering and desired signal (20 mhz apart) at 10% per for 1000 octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db table 32. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14943 rev. *l page 75 of 96 preliminary cyw43340 15.6 wlan 5 ghz transmitter performance specifications note: the specifications in table 33 are measured at the chip port, unless otherwise specified. alternate adjacent channel rejection (difference between interfering and desired signal (40 mhz apart) at 10% per for 1000 c octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?78.5 dbm 32 ? ? db 9 mbps ofdm ?77.5 dbm 31 ? ? db 12 mbps ofdm ?75.5 dbm 29 ? ? db 18 mbps ofdm ?73.5 dbm 27 ? ? db 24 mbps ofdm ?70.5 dbm 24 ? ? db 36 mbps ofdm ?66.5 dbm 20 ? ? db 48 mbps ofdm ?62.5 dbm 16 ? ? db 54 mbps ofdm ?61.5 dbm 15 ? ? db 65 mbps ofdm ?60.5 dbm 14 ? ? db maximum receiver gain ? ? 100 ? db gain control step ? ? 3 ? db rssi accuracy d range ?98 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? 610? db receiver cascaded noise figure at maximum gain ? 5.0 ? db a.derate ? by ? 1.5 ? db ? for ? ?30 ? c ? to ? ?10c ? and ? 55c ? to ? 85c. b.the ? cellular ? standard ? listed ? for ? each ? band ? indicates ? the ? type ? of ? modulation ? used ? to ? generate ? the ? interfering ? signal ? in ? that ? band ? for ? the ? purpose ? of ? this ? test. it ? is ? not ? intended ? to ? indicate ? any ? specific ? usage ? of ? each ? band ? in ? any ? specific ? country. c.for ? 65 ? mbps, ? the ? size ? is ? 4096. d.the ? minimum ? and ? maximum ? values ? shown ? have ? a ? 95% ? confidence ? level. table 33. wlan 5 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz transmitted power in cellular and fm bands (?18 dbm at the antenna port, >90% duty cycle, ofdm) a 76?108 mhz fm rx ? < ?168 ? dbm/hz 776?794 mhz ? ? ?168 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?170 ? dbm/hz 925?960 mhz e-gsm ? ?170 ? dbm/hz 1570?1580 mhz gps ? ?168 ? dbm/hz 1805?1880 mhz gsm1800 ? ?169 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?169 ? dbm/hz 2110?2170 mhz wcdma ? ?169 ? dbm/hz 2400?2483 mhz bt/wlan ? ?166 ? dbm/hz 2300?2690 lte ? ?167 ? dbm/hz harmonic level (at 17 dbm) 9.8?11.570 ghz 2nd harmonic ? ?48.6 ? dbm/mhz table 32. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14943 rev. *l page 76 of 96 preliminary cyw43340 15.7 general spurious emissions specifications tx power at chip port for highest power level setting at 25c, vbat = 3.6v, spectral mask and evm compliance b 6 mbps ? 19 ? dbm 54 mbps ? 17 ? dbm mcs0 (20 mhz) ? 19.5 ? dbm mcs7 (20 mhz) ? 16.5 ? dbm mcs7 (40 mhz) ? 16.5 ? dbm mcs7 (20 mhz, sgi) ? 16.5 ? dbm mcs7 (40 mhz, sgi) ? 16.5 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.7 ? degrees tx power control dynamic range ?30??db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss z o = 50 ? ?6?db a.the ? cellular ? standards ? listed ? indicate ? only ? typical ? usages ? of ? that ? band ? in ? some ? countries. ? other ? standards ? may ? also ? be ? used ? within ? those ? bands. b.derate ? by ? 2db ? for ? ?30c ? to ? ?10c ? and ? 55c ? to ? 85c. table 34. general spurious emissions specifications parameter condition/notes min typ max unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ? ?62 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ? ?47 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ? ?53 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ? ?53 dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?78 ?63 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?68.5 a a.for ? frequencies ? other ? than ? 3.2 ? ghz, ? the ? emissions ? value ? is ? ?96 ? dbm. ? the ? value ? presented ? in ? table ? is ? the ? result ? of ? lo ? leakage ? at ? 3.2 ? ghz. ?53 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?96 ?53 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?96 ?53 dbm table 33. wlan 5 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14943 rev. *l page 77 of 96 preliminary cyw43340 16. internal regulator electrical specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. functional operation is not guarant eed outside of the specification limits provided in this section. 16.1 core buck switching regulator table 35. core buck switching regulator (cbuck) specifications specification notes min typ max units input supply voltage (dc), vbat dc voltage range inclusive of disturbances. 2.9 3.6 4.8 a v pwm mode switching frequency, fsw forced pwm without fll enabled. 2.8 4 5.2 mhz forced pwm with fll enabled. 3.6 4 4.4 mhz pwm output current ? ? ? 372 b ma output current limit ? ? 1390 ? ma output voltage range programmable, 30 mv steps. default = 1.35v (bits = 0000). 1.2 1.35 1.5 volts pwm output voltage dc accuracy includes load and line regulation. forced pwm mode. ?4 ? 4 % total dc accuracy after trim. ?2 ? 2 % pwm ripple voltage, static measure with 20 mhz bw limit. static load. max ripple based on: vbat < 4.8v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor, l > 1.05 h, capacitor + board total-esr < 20 m ? , cout > 1.9 f, esl < 200 ph. ? 7 20 mvpp pwm mode peak efficiency (peak efficiency is at 200 ma load. the following conditions apply to all inductor types: forced pwm, 200 ma, vout = 1.35v, vbat = 3.6v, fsw = 4 mhz, at 25c.) 2.5 x 2 mm lqm2hpn2r2ng0, l = 2 h, dcr = 80 m ? 25%, acr < 1 ? . 79 85 ? % 0805-size lqm21pn2r2ngc, l = 2.1 h, dcr=230 m ? 25%, acr < 2 ? . 78 84 ? % 0603-size mipstz1608d2r2b, l = 1 h, dcr = 240 m ? 25%, acr < 2 ? . 74 81 ? % pfm mode efficiency 10 ma load current, vout = 1.35v, vbat = 3.6v, 20c cap + board total-esr < 20 m ? , cout = 4.7 f, esl < 200 ph, fll= off 0603-size mipstz1608d2r2b, l = 2.2 h, dcr = 240 m ? 25%, acr < 2 ? . 67 77 ? % lpom efficiency 1 ma load current, vout = 1.35v, vbat = 3.6v, 20c cap + board total-esr < 20 m ? , cout = 4.7 f, esl < 200 ph, fll = off 0603-size mipstz1608d2r2b, l = 2.2 h, dcr = 240 ? 25%, acr < 2 ? . 55 65 ? % start-up time from power down vio already on and steady. time from reg_on rising edge to cldo reaching 1.2v. includes 256 sec typical vddc_ok_o delay. ? 903 1106 s
document number: 002-14943 rev. *l page 78 of 96 preliminary cyw43340 16.2 3.3v ldo (ldo3p3) external inductor, l c ? ? 2.2 ? h external output capacitor, cout c ceramic, x5r, 0402, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f, murata ? grm155r60j475m 2 d 4.7 ? f external input capacitor, cin c for sr_vddbatp5v pin. ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f, murata grm155r60j475m. 0.67 d 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? 100,000 s a.the ? maximum ? continuous ? voltage ? is ? 4.8v. ? voltages ? up ? to ? 5.5v ? for ? up ? to ? 10 ? seconds, ? cumulative ? duration, ? over ? the ? lifetime ? of ? the ? device ? are ? allowed. ? volt- ages ? as ? high ? as ? 5.0v ? for ? up ? to ? 250 ? seconds, ? cumulative ? duration, ? over ? the ? lifetime ? of ? the ? device ? are ? allowed. b.at ? junction ? temperature ? 125c. c.refer ? to ? pcb layout guidelines and component selection for optimized pmu performance ? (4334-an200-r) ? for ? component ? selection ? details. d.the ? minimum ? value ? refers ? to ? the ? residual ? capacitor ? value ? after ? taking ? into ? account ? part-to-part ? tolerance, ? dc-bias, ? temperature, ? and ? aging. table 36. ldo3p3 specifications parameters conditions min. typ. max. units input supply voltage, vin minimum = vo+0.2v = 3.5v (for vo = 3.3v) dropout voltage requirement must be met under max load for perfor- mance specs. 2.93.64.8v nominal output voltage, vo default = 3.3v ? 3.3 ? v output voltage program- mability range accuracy at any step (including line/load regulation), load > 0.1 ma 2.4 ?5 ?3.4 +5 v % dropout voltage at maximum load ? ? 200 mv output current ? 0.001 ? 450 ma quiescent current no load; vin = vo + 0.2v maximum load @ 450ma; vin = vo + 0.2v ?66 4 85 4.5 a ma leakage current powerdown mode ( at 85c junction temperature) ? 1.5 5 a line regulation vin from (vo + 0.2v) to 4.8v, maximum load ? 3.5 mv/v load regulation load from 1?450 ma, vin = 3.6v ? 0.3 0.45 mv/ma load step error load from 1ma-200ma-400ma in 1 q5s and 400ma-200ma-1ma in 1 s; vin (vo + 0.2v); co = 4.7 f ??70mv psrr vbat 3.6v, vo = 3.3v, co = 4.7 f, maximum load, 100 hz to 100 khz 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 160 250 s output current limit ? ? 800 ma in-rush current vin = vo + 0.2v to 4.8v, co = 4.7 f, no load ? 280 ma external output capacitor, co ceramic, x5r, 0402, (esr: 5m-240mohm), 10%, 10v 1.0 4.7 5.64 f external input capacitor for sr_vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, 10%, 10v. not needed if sharing vbat cap 4.7 f with sr_vddbatp5v. ?4.7?f table 35. core buck switching regula tor (cbuck) specifications (cont.) specification notes min typ max units
document number: 002-14943 rev. *l page 79 of 96 preliminary cyw43340 16.3 2.5v ldo (ldo2p5) 16.4 hsicdvdd ldo table 37. ldo2p5 specifications specification notes min. typ. max. unit input supply voltage min= 2.52+0.15=2.67v dropout voltage requirement must be met under the maximum load for performance specifications. 2.93.64.8v output current ? ? ? 70 ma output voltage, vo default = 2.52v 2.4 2.52 3 . 4v dropout voltage at max load 150 mv output voltage dc accuracy include line/load regulation ?5 +5 % quiescent current no load ? 8 ? a line regulation vin from (vo + 0.15v) to 4.8v, maximum load ?11 11 mv load regulation load from 1?70 ma (subject to parasitic resistance of package and board). vin = 2.52 + 0.15v to 4.8v ? 1531mv leakage current powerdown mode. at junction temp 85c ? ? 5 a psrr vbat 3.6v, vo = 2.52v, co = 2.2 f, maximum load, 100 hz to 100 khz 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? ? 260 s in-rush current during turn-on from its output capacitor in fully-discharged state ? ? 100 ma external output capacitor, co ceramic, x5r, 0402, (esr: 5m-240mohm), 20%, 6.3v 0.7 a a.minimum ? cap ? value ? refers ? to ? residual ? cap ? value ? after ? taking ? into ? account ? part?to?part ? tolerance, ? dc?bias, ? temperature, ? aging 2.2 2.64 f external input capacitor for sr_vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, 10%, 10v. not needed if sharing the vbat capacitor 4.7 f with sr_vddbatp5v. ?1?f table 38. hiscdvdd ldo specifications specification notes min typ max units input supply voltage min = 1.2v + 0.1v = 1.3v. dropout voltage requirement must be met under maximum load for performance specifi- cations. 1.3 1.35 1.5 v output current ? ? ? 80 ma output voltage, v o step size 25 mv. default = 1.2v. 1.1 1.2 1.275 v dropout voltage at maximum load. includes 100 m ? routing resistors at input and output. ??100mv output voltage dc accuracy including line/load regulation. ?4 ? 4 % quiescent current no load. dependent on programming. ldo_cntl_i[43], ldo_cntl_i[41] to support different external capacitor loads. ?182?a psrr at 1 khz input 1.35v, 50 to 300 pf, v o = 1.2v load: 80 ma load: 40 ma 24 39 ?? db db
document number: 002-14943 rev. *l page 80 of 96 preliminary cyw43340 16.5 cldo psrr at 10 khz input 1.35v, 50 to 300 pf, v o = 1.2v load: 80 ma load: 40 ma 24 38 ?? db db psrr at 100 khz input 1.35v, 50 to 300 pf, v o = 1.2v load: 80 ma load: 40 ma 15 27 ?? db db output capacitor, c o internal capacitor = sum of supply decoupling caps and supply-to-ground routing parasitic capacitance. output capacitor dependent on programming. ?1000?pf table 39. cldo specifications specification notes min typ max units input supply voltage, v in min = 1.2 + 0.1v = 1.3v. dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v, load from 0.1?150 ma 1.1 1.2 1.275 v dropout voltage at max load ? ? 100 mv output voltage dc accuracy a a.load ? from ? 0.1 ? to ? 150 ? ma. includes line/load regulation ?4 ? +4 % after trim, load from 0.1?150 ma, includes line/load regulation. v in > v o + 0.1v. ?2 ? +2 % quiescent current no load ? 10 ? a line regulation v in from (v o + 0.1v) to 1.5v, maximum load ? ? 7 mv/v load regulation load from 1 ma to 150 ma ? 15 25 v/ma leakage current power-down ? ? 10 a psrr @1 khz, vin 1.5v, c o = 1 f 20 ? db start-up time of pmu vio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. includes 256 s vddc_ok_o delay. ??1106s ldo turn-on time chip already powered up. ? ? 180 s in-rush current during turn-on from its output capacitor in a fully-discharged state ? ? 150 ma external output capacitor, c o b b.refer ? to ? pcb layout guidelines and component selection for optimized pmu performance ? (4334-an200-r) ? for ? component ? selection ? details. total esr: 30 m ? ?200 m ? 0.67 c c.the ? minimum ? value ? refers ? to ? the ? residual ? capacitor ? value ? after ? taking ? into ? account ? the ? part-to-part ? tolerance, ? dc-bias, ? temperature, ? and ? aging. 1 ? f external input capacitor only use an ex ternal input capacitor at the vdd_ldo pin if it is not supplied from the cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ?1?f table 38. hiscdvdd ldo specifications (cont.) specification notes min typ max units
document number: 002-14943 rev. *l page 81 of 96 preliminary cyw43340 16.6 lnldo table 40. lnldo specifications specification notes min typ max units input supply voltage, vin min = 1.2v o + 0.1v = 1.3v. dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 104 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 100 mv output voltage dc accuracy a a.load ? from ? 0.1 ? to ? 104 ? ma. includes line/load regulation, load from 0.1 to 150 ma ?4 ? +4 % quiescent current no load ? 44 ? a line regulation v in from (v o + 0.1v) to 1.5v, max load ? ? 7 mv/v load regulation load from 1 ma to 104 ma ? 15 25 v/ma leakage current power-down ? ? 10 a output noise @30 khz, 60 ma load, c o = 1 f @100 khz, 60 ma load, c o = 1 f ? ? 60 35 nv/root-hz nv/root-hz psrr @ 1khz, input > 1.3v, c o = 1 f, v o = 1.2v 20 ? ? db start-up time of pmu vio up and stead y. time from the reg_on rising edge to the lnldo reaching 1.2v. includes 256 s vddc_ok_o delay. ? ? 1106 s ldo turn-on time chip already powered up. ? ? 180 s in-rush current during turn -on from its output capacit or in a fully-discharged state ??150ma external output capacitor, c o b b.refer ? to ? pcb layout guidelines and component selection for optimized pmu performance ? (4334-an200-r) ? for ? component ? selection ? details. total esr (trace/capacitor): 30?200 m ? 0.67 c c.the ? minimum ? value ? refers ? to ? the ? residual ? capacitor ? value ? after ? taking ? into ? account ? the ? part-to-part ? tolerance, ? dc-bias, ? temperature, ? and ? aging. 1 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from the cbuck output. total esr (trace/capacitor): 30?200 m ? ?1?f
document number: 002-14943 rev. *l page 82 of 96 preliminary cyw43340 17. system power consumption note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, t hese values apply for the conditions specified in table 24: ?recommended operating conditions and dc characteristics,? on page 58 . 17.1 wlan current consumption the wlan current consumption measurements are shown in ta b l e 4 1 . all values in ta b l e 4 1 are with the bluetooth core in re set (that is, bluetooth is off). table 41. typical wlan power consumption mode bandwidth (mhz) band (ghz) vbat = 3.6v, vddio = 1.8v, t a 25c vbat (ma) vio a (a) a.vio ? is ? specified ? with ? all ? pins ? idle ? and ? not ? driving ? any ? loads. sleep modes leakage (off) ? ? 0.004 220 sleep b b.idle ? between ? beacons. ??0.005 220 ieee power save, dtim 1 c c.beacon ? interval ? = ? 100 ms; ? beacon ? duration ? = ? 1.9 ms ? @ ? 1mbps ? (integrated ? sleep ? + ? wakeup ? + ? beacon) ??1.06 220 ieee power save dtim 3 d d.beacon ? interval ? = ? 300 ms; ? beacon ? duration ? = ? 1.9 ms ? @ ? 1mbps ? (integrated ? sleep ? + ? wakeup ? + ? beacon) ??0.321 220 active modes rx (listen) e, f e.carrier ? sense ? (cca) ? when ? no ? carrier ? present. f.carrier ? sense ? (cs) ? detect/packet ? rx. ? ? 44.4 200 rx (active) f, g, h g.applicable ? to ? all ? supported ? rates. h.duty ? cycle ? = ? 100% ? ? 57.7 200 tx cck, 11 mbps (20.5 dbm @ chip) h, i, j i.tx ? output ? power ? is ? measured ? at ? the ? chip-out ? side. j.the ? items ? of ? active ? modes ? are ? measured ? under ? the ? real ? association/throughput ? with ? the ? wireless ? ap. ht20 2.4 325 200 tx, mcs7 (17.5 dbm @ chip) h, i, j ht20 2.4 254 200 tx, mcs7 (17.5 dbm @ chip) h, i, j ht40 2.4 270 200 tx ofdm, 54 mbps (18 dbm @ chip) h, i, j ht20 2.4 263 200 tx, mcs7 (15 dbm @ chip) h, i, j ht20 5 261 200 tx, mcs7 (15 dbm @ chip) h, i, j ht40 5 283 200 tx ofdm, 54 mbps (16 dbm @ chip) h, i, j ht20 5 271 200
document number: 002-14943 rev. *l page 83 of 96 preliminary cyw43340 17.2 bluetooth and ble current consumption the bluetooth current consumpt ion measurements are shown in ta b l e 4 2 . the wlan core is in reset (wl_reg_on = low) for all measurements provided in ta b l e 4 2 . the bt current consumption numbers are meas ured based on gfsk tx output power = 8 dbm. table 42. bluetooth current consumption operating mode vbat (3.6v) vddio (1.8v) unit sleep 6 133 a sco hv3 master 10.1 ? ma 3dh5/3dh1 master 18.1 ? ma dm1/dh1 master 22.9 ? ma dm3/dh3 master 27.0 ? ma dm5/dh5 master 28.3 ? ma 2ev3 7.5 0.1 ma ble scan a a.no ? devices ? present; ? 1.28 ? second ? interval ? with ? a ? scan ? window ? of ? 11.25 ? ms. 169 131 a ble connected (1 second) 43 132 a
document number: 002-14943 rev. *l page 84 of 96 preliminary cyw43340 18. interface timing an d ac characteristics 18.1 sdio timing 18.1.1 sdio default mode timing sdio default mode timing is shown by the combination of figure 31 and table 43 . figure 31. sdio bus timing (default mode) table 43. sdio bus timing a parameters (default mode) a.timing ? is ? based ? on ? cl ? ? ? 40pf ? load ? on ? cmd ? and ? data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b.min(vih) ? = ? 0.7 ? ? vddio ? and ? max(vil) ? = ? 0.2 ? ? vddio. frequency ? data transfer mode fpp 0 ? 25 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock low time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5 ? ? ns input hold time tih 5 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly 0 ? 14 ns output delay time ? identification mode todly 0 ? 50 ns t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document number: 002-14943 rev. *l page 85 of 96 preliminary cyw43340 18.1.2 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 32 and table 44 . figure 32. sdio bus timing (high-speed mode) table 44. sdio bus timing a parameters (high-speed mode) a.timing ? is ? based ? on ? cl ? ? ? 40pf ? load ? on ? cmd ? and ? data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b.min(vih) ? = ? 0.7 ? ? vddio ? and ? max(vil) ? = ? 0.2 ? ? vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 7 ? ? ns clock high time twh 7 ? ? ns clock rise time ttlh ? ? 3 ns clock low time tthl ? ? 3 ns inputs: cmd, dat (referenced to clk) input setup time tisu 6 ? ? ns input hold time tih 2 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% ? vdd t oh sdio_clk
document number: 002-14943 rev. *l page 86 of 96 preliminary cyw43340 18.2 hsic interface specifications 18.3 jtag timing table 45. hsic timing parameters parameter symbol minimum typical maximum unit comments hsic signaling voltage v dd 1.1 1.2 1.3 v ? i/o voltage input low v il ?0.3 ? 0.35 v dd v? i/o voltage input high v ih 0.65 v dd ?v dd + 0.3 v ? i/o voltage output low v ol ??0.25 v dd v? i/o voltage output high v oh 0.75 v dd ??v? i/o pad drive strength o d 40 ? 60 ? controlled output impedance driver i/o weak keepers i l 20 ? 70 a? i/o input impedance z i 100??k ? ? total capaci tive load a a.total ? capacitive ? load ? (c l ), ? includes ? device ? input/output ? capacitance, ? and ? capacitance ? of ? a ? 50 ?? pcb ? trace ? with ? a ? length ? of ? 10 cm. c l 3?14pf? characteristic trace impedance t i 45 50 55 ? ? circuit board trace length t l ??10cm? circuit board trace propagation skew b b.maximum ? propagation ? delay ? skew ? in ? strobe ? or ? data ? with ? respect ? to ? each ? other. ? the ? trace ? delay ? should ? be ? matched ? between ? strobe ? and ? data ? to ? ensure that ? the ? signal ? timing ? is ? within ? specification ? limits ? at ? the ? receiver. t s ??15ps? strobe frequency c c.jitter ? and ? duty ? cycle ? are ? not ? separately ? specified ? parameters, ? they ? are ? incorporated ? into ? the ? values ? in ? the ? table ? above. f strobe 239.988 240 240.012 mhz 500 ppm slew rate (rise and fall) strobe and data c t slew 0.60 v dd 1.0 1.2 v/ns averaged from 30% ~ 70% points receiver data setup time (with respect to strobe) c t s 300 ? ? ps measured at the 50% point receiver data hold time (with respect to strobe) c t b 300 ? ? ps measured at the 50% point table 46. jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ?
document number: 002-14943 rev. *l page 87 of 96 preliminary cyw43340 19. power-up sequence and timing 19.1 sequencing of reset and regulator control signals the cyw43340 has three signals that allow the host to control pow er consumption by enabling or disabling the bluetooth, wlan, and internal regulator blocks. these signals are described below. additionally, di agrams are provided to i ndicate pro per sequen cing of the signals for various operational states (see figure 33 , figure 34 on page 88 , and figure 35 and figure 36 on page 89 ). the timing values indicated are minimum required values; longer delays are also acceptable. the wl_reg_on and bt_reg_on signals are ored in the cyw43340 . the diagrams show both signals going high at the same time (as would be the case if both reg signals were controlled by a single host gpio). if two independent host gpios are used (one for wl_reg_on and one for bt_reg_on), then only one of the two signals needs to be high to enable the cyw43340 regulators. the cyw43340 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold (see table 24: ?recommended operating conditions and dc characteristics,? on page 58 ). wait at least 150 ms after vddc and vddio are available before initiating sdio accesses. vbat should not rise faster than 40 s. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. 19.1.1 description of control signals wl_reg_on : used by the pmu to power up the wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw43340 regulators. when this pin is high, the regulato rs are enabled and the wlan section is out of reset. when this pin is low the wlan section is in reset. if both the bt_r eg_on and wl_reg_on pins are lo w, the regulators are disabled. bt_reg_on : used by the pmu (or-gated with wl_reg_on) to powe r up the internal cyw43340 regulators. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. when this pin is low and wl_reg_on is high, the bt section is in reset. note: for both the wl_reg_on and bt_r eg_on pins, there should be at le ast a 10 msec time delay between consecutive toggles (where both signals have been driven lo w). this is to allow time for the cbuck regulator to discharge. if this delay is not followed, then there may be a vddio in-rush current on the order of 36 ma during the next pmu cold start. 19.1.2 control signal timing diagrams figure 33. wlan = on, bluetooth = on 32.678 khz ? sleep ? clock vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles *notes: 1. ? vbat ? should ? not ? rise ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 100 ? milliseconds. 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio . ?? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-14943 rev. *l page 88 of 96 preliminary cyw43340 figure 34. wlan = off, bluetooth = off figure 35. wlan = on, bluetooth = off 32.678 khz ? sleep ? clock vbat* vddio wl_reg_on bt_reg_on *notes: 1. ? vbat ? should ? not ? rise ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 100 ? milliseconds. 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio . ?? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high. 32.678 ? khz ? sleep ? clock vbat vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles *notes: 1. ? vbat ? should ? not ? rise ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 100 ? milliseconds. 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio . ?? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-14943 rev. *l page 89 of 96 preliminary cyw43340 figure 36. wlan = off, bluetooth = on 32.678 khz ? sleep ? clock vbat vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles *notes: 1. ? vbat ? should ? not ? rise ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 100 ? m illiseconds. 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio . ?? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-14943 rev. *l page 90 of 96 preliminary cyw43340 20. package information 20.1 package thermal characteristics 20.2 junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi?j t ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta?j c ( ? jc ). the reason for this is that ? jc assumes that all the power is dissipated through the top surface of the package case. in actu al applications, some of the power is dissipated through the bot tom and sides of the package. ? jt takes into account power dissipated through the t op, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x ? jt where: t j = junction temperature at steady-state condition (c) t t = package case top center temperat ure at steady-stat e condition (c) p = device power dissipation (watts) ? jt = package thermal characteri stics; no airflow (c/w) 20.3 environmental characteristics for environmental char acteristics data, see table 22: ?environmental ratings,? on page 57 . table 47. package thermal characteristics a a. ? no ? heat ? sink, ? ta ? = ? 70c. ? this ? is ? an ? estimate, ? based ? on ? a ? 4-layer ? pcb ? that ? conforms ? to ? eia/jesd51?7 ? (101.6 mm 101.6 mm 1.6 mm) ? and ? p ? = ? 1.198w continuous ? dissipation. characteristic wlbga ? ja (c/w) (value in still air) 36.8 ? jb (c/w) 5.93 ? jc (c/w) 2.82 ? jt (c/w) 9.26 ? jb (c/w) 16.93 maximum junction temperature t j 114.08 maximum power dissipation (w) 1.198
document number: 002-14943 rev. *l page 91 of 96 preliminary cyw43340 21. mechanical information figure 37. 141-ball wlbga pack age mechanical information
document number: 002-14943 rev. *l page 92 of 96 preliminary cyw43340 figure 38. wlbga keep-out areas for pcb layout?bottom view note: no top-layer metal is allowed in keep-out areas.
document number: 002-14943 rev. *l page 93 of 96 preliminary cyw43340 22. ordering information part number package description operating ambi- ent temperature cyw43340xkubg 141 ball wlbga (5.67 mm 4.47 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bt 4.0 ?30c to +85c cyw43340hkubg 141 ball wlbga (5.67 mm 4.47 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bt 4.0 + bsp ?30c to +85c
document number: 002-14943 rev. *l page 94 of 96 preliminary cyw43340 document history document title: cyw43340 single-chip, dual-band (2.4 ghz/ 5 ghz) ieee 802.11 a/b/g/n mac/baseband/radio with inte- grated bluetooth 4.0 document number: 002-14943 revision ecn orig. of change submission date description of change ** - - 07/09/2012 43340?ds100-r: ? initial release *a - - 12/21/2012 43340?ds101-r: updated: ? hci high-speed uart: h4+ mode no longer supported. ? general description on page 1. ? ?ieee 802.11x key features? on page 5: shared bluetooth and 2.4 ghz wlan signal path. ? figure 11: ?startup signaling sequence,? on page 54. ? ?external coexistence interface? on page 80. ? table 26: ?wlbga and wlcsp si gnal descriptions,? on page 127. ? table 27: ?wlan gpio functions an d strapping options (advance in- formation),? on page 140. ? table 31: ?i/o states,? on page 145 . ? table 32: ?absolute maximum ratings,? on page 149. ? table 36: ?bluetooth receiver rf specifications,? on page 154. ? table 37: ?bluetooth transmitter rf specifications,? on page 158. ? table 53: ?typical wlan power consumption,? on page 185. ? table 54: ?bluetooth and fm current consumption,? on page 187. *b - - 04/22/2013 43340?ds102-r: updated: ? figure 1: ?functional block diagram,? on page 1. ? aes feature description on page 5. ? vbat voltage range changed from 2.3?4.8v to 2.9?4.8v. ? figure 4: ?typical power topology,? on page 29. ? ?link control layer? on page 51: substates. ? table 33: ?bluetooth receiver rf specifications,? on page 131. ? figure 52: ?wlan port locations (5 ghz),? on page 142. ? table 34: ?bluetooth transmitter rf s pecifications,? on page 135: power control step. ? table 36: ?ble rf specificat ions,? on page 136: rx sense. ? table 37: ?fm receiver specifications,? on page 137. ? table 39: ?wlan 2.4 ghz receiver performance specifications,? on page 144. ? table 40: ?wlan 2.4 ghz transmitter performance specifications,? on page 148. ? table 42: ?wlan 5 ghz transmitter performance specifications,? on page 153. ? table 50: ?typical wlan power consumption,? on page 162. *c - 08/30/0213 43340?ds103-r: ? removed ?preliminary? from the document type. *d - - 12/03/2013 43340?ds104-r: updated: ? proprietary protocols in ?standards compliance? on page 21. ? table 24: ?esd specifications,? on page 102. ? table 33: ?wlan 2.4 ghz transmitter performance specifications,? on page 124. ? table 35: ?wlan 5 ghz transmitter performance specifications,? on page 129. *e - - 02/14/2014 43340?ds105-r: updated: ? section 26: ?ordering information,? on page 194.
document number: 002-14943 rev. *l page 95 of 96 preliminary cyw43340 *f - - 03/04/0214 43340?ds106-r: ? figure 38: ?141-bump cyw43340 wlbga ball map (bottom view),? on page 58 and table 18: ?wlbga signal descriptions,? on page 59: up- dated signal names for no connect, vddc, vddio, vss, vssc, and wrf_pa5g_vbat_gnd3p3 pins. *g - - 04/07/2014 43340?ds107-r: updated: ? [43341]figure 48: ?nfc boot-up s equence (secure patch download) from snooze,? on page 117 ? [43341]?nfc operation requirement? on page 119 ? table 28: ?wlan gpio functions an d strapping options (advance in- formation),? on page 144 ? title change (2.5 ghz to 2.4 ghz) for figure 55 on page 169 *h - - 07/07/2014 43340?ds108-r: updated: ? figure 65: ?wlbga keep-out areas for pcb layout ? bottom view,? on page 177 *i - - 01/28/2015 43340?ds109-r: updated: ? table 18: ?wlbga signal descriptions,? on page 59 *j - - 09/10/2015 43340?ds110-r: updated: ? table 32: ?wlan 2.4 ghz receiver performance specifications,? on page 85 *k 5529544 utsv 11/23/2016 updated to cypress template *l 5675330 utsv 03/28/2017 removed fm and gspi sections throughout the document. document title: cyw43340 single-chip, dual-band (2.4 ghz/ 5 ghz) ieee 802.11 a/b/g/n mac/baseband/radio with inte- grated bluetooth 4.0 document number: 002-14943
document number: 002-14943 rev. *l revised march 28, 2017 page 96 of 96 ? cypress semiconductor corporation, 2012-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. preliminary cyw43340 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 96

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